Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LDO_RAMP_UP_UNIT_IN_CYCLES      64 /* 64 cycles per step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LDO_RAMP_UP_FREQ_IN_MHZ         24 /* cycle based on 24M OSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LDO_POWER_GATE			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LDO_FET_FULL_ON			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct anatop_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u32 delay_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	int delay_bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	int delay_bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct regulator_desc rdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned int old_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	unsigned int new_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	/* check whether need to care about LDO ramp up speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		 * the delay for LDO ramp up time is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		 * based on the register setting, we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		 * to calculate how many steps LDO need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		 * ramp up, and how much delay needed. (us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		regmap_read(reg->regmap, anatop_reg->delay_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		val = (val >> anatop_reg->delay_bit_shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			((1 << anatop_reg->delay_bit_width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int anatop_regmap_enable(struct regulator_dev *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return regulator_set_voltage_sel_regmap(reg, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int anatop_regmap_disable(struct regulator_dev *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int anatop_regmap_is_enabled(struct regulator_dev *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 					      unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		anatop_reg->sel = selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ret = regulator_set_voltage_sel_regmap(reg, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		anatop_reg->sel = selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return anatop_reg->sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return regulator_get_voltage_sel_regmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	sel = regulator_get_voltage_sel_regmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (sel == LDO_FET_FULL_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		WARN_ON(!anatop_reg->bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	else if (sel != LDO_POWER_GATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		WARN_ON(anatop_reg->bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	*enable = anatop_reg->bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (enable == anatop_reg->bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	anatop_reg->bypass = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return regulator_set_voltage_sel_regmap(reg, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct regulator_ops anatop_rops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct regulator_ops anatop_core_rops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.enable = anatop_regmap_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.disable = anatop_regmap_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.is_enabled = anatop_regmap_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.set_voltage_sel = anatop_regmap_core_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.get_voltage_sel = anatop_regmap_core_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.get_bypass = anatop_regmap_get_bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.set_bypass = anatop_regmap_set_bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int anatop_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct device_node *anatop_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct regulator_desc *rdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct anatop_regulator *sreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct regulator_init_data *initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u32 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 vol_bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u32 vol_bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u32 min_bit_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 min_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 max_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!sreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	rdesc = &sreg->rdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	rdesc->type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	rdesc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	of_property_read_string(np, "regulator-name", &rdesc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (!rdesc->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		dev_err(dev, "failed to get a regulator-name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	initdata = of_get_regulator_init_data(dev, np, rdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (!initdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	initdata->supply_regulator = "vin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	anatop_np = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (!anatop_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	regmap = syscon_node_to_regmap(anatop_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	of_node_put(anatop_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		dev_err(dev, "no anatop-reg-offset property set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ret = of_property_read_u32(np, "anatop-vol-bit-width", &vol_bit_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		dev_err(dev, "no anatop-vol-bit-width property set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ret = of_property_read_u32(np, "anatop-vol-bit-shift", &vol_bit_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		dev_err(dev, "no anatop-vol-bit-shift property set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	ret = of_property_read_u32(np, "anatop-min-bit-val", &min_bit_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dev_err(dev, "no anatop-min-bit-val property set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = of_property_read_u32(np, "anatop-min-voltage", &min_voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_err(dev, "no anatop-min-voltage property set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = of_property_read_u32(np, "anatop-max-voltage", &max_voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		dev_err(dev, "no anatop-max-voltage property set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* read LDO ramp up setting, only for core reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	of_property_read_u32(np, "anatop-delay-reg-offset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			     &sreg->delay_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	of_property_read_u32(np, "anatop-delay-bit-width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			     &sreg->delay_bit_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	of_property_read_u32(np, "anatop-delay-bit-shift",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			     &sreg->delay_bit_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	rdesc->n_voltages = (max_voltage - min_voltage) / 25000 + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			    + min_bit_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	rdesc->min_uV = min_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	rdesc->uV_step = 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	rdesc->linear_min_sel = min_bit_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	rdesc->vsel_reg = control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	rdesc->vsel_mask = ((1 << vol_bit_width) - 1) << vol_bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	rdesc->min_dropout_uV = 125000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	config.init_data = initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	config.driver_data = sreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	config.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	config.regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Only core regulators have the ramp up delay configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (control_reg && sreg->delay_bit_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		rdesc->ops = &anatop_core_rops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			dev_err(dev, "failed to read initial state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		sreg->sel = (val & rdesc->vsel_mask) >> vol_bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		if (sreg->sel == LDO_FET_FULL_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			sreg->sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			sreg->bypass = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		 * In case vddpu was disabled by the bootloader, we need to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		 * a sane default until imx6-cpufreq was probed and changes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		 * voltage to the correct value. In this case we set 1.25V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		if (!sreg->sel && !strcmp(rdesc->name, "vddpu"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			sreg->sel = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		/* set the default voltage of the pcie phy to be 1.100v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		if (!sreg->sel && !strcmp(rdesc->name, "vddpcie"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			sreg->sel = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (!sreg->bypass && !sreg->sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		u32 enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		rdesc->ops = &anatop_rops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (!of_property_read_u32(np, "anatop-enable-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 					  &enable_bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			anatop_rops.enable  = regulator_enable_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			anatop_rops.disable = regulator_disable_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			anatop_rops.is_enabled = regulator_is_enabled_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			rdesc->enable_reg = control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			rdesc->enable_mask = BIT(enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/* register regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	rdev = devm_regulator_register(dev, rdesc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			dev_dbg(dev, "failed to register %s, deferring...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 				rdesc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			dev_err(dev, "failed to register %s\n", rdesc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	platform_set_drvdata(pdev, rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct of_device_id of_anatop_regulator_match_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	{ .compatible = "fsl,anatop-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{ /* end */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct platform_driver anatop_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.name	= "anatop_regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.of_match_table = of_anatop_regulator_match_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.probe	= anatop_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int __init anatop_regulator_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return platform_driver_register(&anatop_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) postcore_initcall(anatop_regulator_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void __exit anatop_regulator_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	platform_driver_unregister(&anatop_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) module_exit(anatop_regulator_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MODULE_DESCRIPTION("ANATOP Regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_ALIAS("platform:anatop_regulator");