^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * AB8500 peripheral regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * AB8500 supports the following regulators:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * AB8505 supports the following regulators:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/abx500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/abx500/ab8500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regulator/ab8500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * struct ab8500_shared_mode - is used when mode is shared between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * two regulators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @shared_regulator: pointer to the other sharing regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @lp_mode_req: low power mode requested by this regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct ab8500_shared_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ab8500_regulator_info *shared_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool lp_mode_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * struct ab8500_regulator_info - ab8500 regulator information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @dev: device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @desc: regulator description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @shared_mode: used when mode is shared between two regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @load_lp_uA: maximum load in idle (low power) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @update_bank: bank to control on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @update_reg: register to control on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @update_mask: mask to enable/disable and set mode of regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @update_val: bits holding the regulator current mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @update_val_idle: bits to enable the regulator in idle (low power) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @update_val_normal: bits to enable the regulator in normal (high power) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @mode_bank: bank with location of mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @mode_reg: mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @mode_mask: mask for setting mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @mode_val_idle: mode setting for low power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @mode_val_normal: mode setting for normal power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @voltage_bank: bank to control regulator voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @voltage_reg: register to control regulator voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @voltage_mask: mask to control regulator voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @expand_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct ab8500_regulator_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ab8500_shared_mode *shared_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int load_lp_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 update_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 update_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 update_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 update_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 update_val_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 update_val_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 mode_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 mode_val_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 mode_val_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 voltage_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 voltage_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 voltage_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* voltage tables for the vauxn/vintcore supplies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const unsigned int ldo_vauxn_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 1300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 1400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 1850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 1900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 2650000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 2700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 2750000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 2900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const unsigned int ldo_vaux3_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 2100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 2750000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 2790000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 2910000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const unsigned int ldo_vaux56_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 2200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 2790000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const unsigned int ldo_vintcore_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 1225000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 1275000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 1300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 1325000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 1350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const unsigned int fixed_1200000_voltage[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const unsigned int fixed_1800000_voltage[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const unsigned int fixed_2000000_voltage[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const unsigned int fixed_2050000_voltage[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 2050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const unsigned int ldo_vana_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 1075000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 1125000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 1150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 1175000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 1225000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const unsigned int ldo_vaudio_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 2100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 2200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 2300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 2400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 2600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static DEFINE_MUTEX(shared_mode_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct ab8500_shared_mode ldo_anamic1_shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct ab8500_shared_mode ldo_anamic2_shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int ab8500_regulator_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = abx500_mask_and_set_register_interruptible(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) info->update_bank, info->update_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) info->update_mask, info->update_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_err(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "couldn't set enable bits for regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_vdbg(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) info->desc.name, info->update_bank, info->update_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) info->update_mask, info->update_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int ab8500_regulator_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = abx500_mask_and_set_register_interruptible(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) info->update_bank, info->update_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) info->update_mask, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "couldn't set disable bits for regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_vdbg(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) info->desc.name, info->update_bank, info->update_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) info->update_mask, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = abx500_get_register_interruptible(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) info->update_bank, info->update_reg, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "couldn't read 0x%x register\n", info->update_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_vdbg(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) " 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) info->desc.name, info->update_bank, info->update_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) info->update_mask, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (regval & info->update_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static unsigned int ab8500_regulator_get_optimum_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct regulator_dev *rdev, int input_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int output_uV, int load_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (load_uA <= info->load_lp_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mode = REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mode = REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 bank, reg, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bool lp_mode_req = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (info->mode_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bank = info->mode_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) reg = info->mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mask = info->mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bank = info->update_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg = info->update_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mask = info->update_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (info->shared_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mutex_lock(&shared_mode_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (info->shared_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) lp_mode_req = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (info->mode_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val = info->mode_val_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val = info->update_val_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (info->shared_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct ab8500_regulator_info *shared_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) shared_regulator = info->shared_mode->shared_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!shared_regulator->shared_mode->lp_mode_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Other regulator prevent LP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) info->shared_mode->lp_mode_req = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) lp_mode_req = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (info->mode_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val = info->mode_val_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) val = info->update_val_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = abx500_mask_and_set_register_interruptible(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bank, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "couldn't set regulator mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_vdbg(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "%s-set_mode (bank, reg, mask, value): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "0x%x, 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) info->desc.name, bank, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!info->mode_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) info->update_val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (info->shared_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) info->shared_mode->lp_mode_req = lp_mode_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (info->shared_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mutex_unlock(&shared_mode_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 val_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u8 val_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Need special handling for shared mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (info->shared_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (info->shared_mode->lp_mode_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (info->mode_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Dedicated register for handling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = abx500_get_register_interruptible(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) info->mode_bank, info->mode_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val = val & info->mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) val_normal = info->mode_val_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) val_idle = info->mode_val_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Mode register same as enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) val = info->update_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) val_normal = info->update_val_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val_idle = info->update_val_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (val == val_normal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) else if (val == val_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int ret, voltage_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) voltage_shift = ffs(info->voltage_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = abx500_get_register_interruptible(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) info->voltage_bank, info->voltage_reg, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "couldn't read voltage reg for regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_vdbg(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "%s-get_voltage (bank, reg, mask, shift, value): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) info->desc.name, info->voltage_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) info->voltage_reg, info->voltage_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) voltage_shift, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return (regval & info->voltage_mask) >> voltage_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret, voltage_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) voltage_shift = ffs(info->voltage_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* set the registers for the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) regval = (u8)selector << voltage_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = abx500_mask_and_set_register_interruptible(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) info->voltage_bank, info->voltage_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) info->voltage_mask, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "couldn't set voltage reg for regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_vdbg(rdev_get_dev(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) " 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) info->desc.name, info->voltage_bank, info->voltage_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) info->voltage_mask, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct regulator_ops ab8500_regulator_volt_mode_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .enable = ab8500_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .disable = ab8500_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .is_enabled = ab8500_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .get_optimum_mode = ab8500_regulator_get_optimum_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .set_mode = ab8500_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .get_mode = ab8500_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .get_voltage_sel = ab8500_regulator_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .set_voltage_sel = ab8500_regulator_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct regulator_ops ab8500_regulator_volt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .enable = ab8500_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .disable = ab8500_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .is_enabled = ab8500_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .get_voltage_sel = ab8500_regulator_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .set_voltage_sel = ab8500_regulator_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct regulator_ops ab8500_regulator_mode_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .enable = ab8500_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .disable = ab8500_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .is_enabled = ab8500_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .get_optimum_mode = ab8500_regulator_get_optimum_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .set_mode = ab8500_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .get_mode = ab8500_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct regulator_ops ab8500_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .enable = ab8500_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .disable = ab8500_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .is_enabled = ab8500_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct regulator_ops ab8500_regulator_anamic_mode_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .enable = ab8500_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .disable = ab8500_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .is_enabled = ab8500_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .set_mode = ab8500_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .get_mode = ab8500_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* AB8500 regulator information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static struct ab8500_regulator_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * Variable Voltage Regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * name, min mV, max mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * update bank, reg, mask, enable val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * volt bank, reg, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [AB8500_LDO_AUX1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .name = "LDO-AUX1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .id = AB8500_LDO_AUX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .volt_table = ldo_vauxn_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .enable_time = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .supply_name = "vin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .update_reg = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .update_mask = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .update_val = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .update_val_idle = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .update_val_normal = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .voltage_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .voltage_reg = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .voltage_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [AB8500_LDO_AUX2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .name = "LDO-AUX2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .id = AB8500_LDO_AUX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .volt_table = ldo_vauxn_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .enable_time = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .supply_name = "vin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .update_reg = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .update_mask = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .update_val = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .update_val_idle = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .update_val_normal = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .voltage_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .voltage_reg = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .voltage_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [AB8500_LDO_AUX3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .name = "LDO-AUX3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .id = AB8500_LDO_AUX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .volt_table = ldo_vaux3_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .enable_time = 450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .supply_name = "vin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .update_reg = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .update_mask = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .update_val = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .update_val_idle = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .update_val_normal = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .voltage_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .voltage_reg = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .voltage_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) [AB8500_LDO_INTCORE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .name = "LDO-INTCORE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .id = AB8500_LDO_INTCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .volt_table = ldo_vintcore_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .enable_time = 750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .update_reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .update_mask = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .update_val = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .update_val_idle = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .update_val_normal = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .voltage_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .voltage_reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .voltage_mask = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * Fixed Voltage Regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * name, fixed mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * update bank, reg, mask, enable val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) [AB8500_LDO_TVOUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = "LDO-TVOUT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .ops = &ab8500_regulator_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .id = AB8500_LDO_TVOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .volt_table = fixed_2000000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .enable_time = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .load_lp_uA = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .update_reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .update_mask = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .update_val = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .update_val_idle = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .update_val_normal = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) [AB8500_LDO_AUDIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .name = "LDO-AUDIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .ops = &ab8500_regulator_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .id = AB8500_LDO_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .enable_time = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .volt_table = fixed_2000000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .update_reg = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .update_mask = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .update_val = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [AB8500_LDO_ANAMIC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = "LDO-ANAMIC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .ops = &ab8500_regulator_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .id = AB8500_LDO_ANAMIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .enable_time = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .volt_table = fixed_2050000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .update_reg = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .update_mask = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .update_val = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [AB8500_LDO_ANAMIC2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = "LDO-ANAMIC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .ops = &ab8500_regulator_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .id = AB8500_LDO_ANAMIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .enable_time = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .volt_table = fixed_2050000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .update_reg = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .update_mask = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .update_val = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [AB8500_LDO_DMIC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .name = "LDO-DMIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .ops = &ab8500_regulator_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .id = AB8500_LDO_DMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .enable_time = 420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .volt_table = fixed_1800000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .update_reg = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .update_mask = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .update_val = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * Regulators with fixed voltage and normal/idle modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [AB8500_LDO_ANA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .name = "LDO-ANA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .ops = &ab8500_regulator_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .id = AB8500_LDO_ANA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .enable_time = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .volt_table = fixed_1200000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .load_lp_uA = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .update_reg = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .update_mask = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .update_val = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .update_val_idle = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .update_val_normal = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* AB8505 regulator information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static struct ab8500_regulator_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * Variable Voltage Regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * name, min mV, max mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * update bank, reg, mask, enable val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * volt bank, reg, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [AB8505_LDO_AUX1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .name = "LDO-AUX1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .id = AB8505_LDO_AUX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .volt_table = ldo_vauxn_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .update_reg = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .update_mask = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .update_val = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .update_val_idle = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .update_val_normal = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .voltage_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .voltage_reg = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .voltage_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [AB8505_LDO_AUX2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .name = "LDO-AUX2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .id = AB8505_LDO_AUX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .volt_table = ldo_vauxn_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .update_reg = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .update_mask = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .update_val = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .update_val_idle = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .update_val_normal = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .voltage_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .voltage_reg = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .voltage_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [AB8505_LDO_AUX3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .name = "LDO-AUX3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .id = AB8505_LDO_AUX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .volt_table = ldo_vaux3_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .update_reg = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .update_mask = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .update_val = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .update_val_idle = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .update_val_normal = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .voltage_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .voltage_reg = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .voltage_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [AB8505_LDO_AUX4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .name = "LDO-AUX4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .id = AB8505_LDO_AUX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .volt_table = ldo_vauxn_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* values for Vaux4Regu register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .update_reg = 0x2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .update_mask = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .update_val = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .update_val_idle = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .update_val_normal = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* values for Vaux4SEL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .voltage_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .voltage_reg = 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .voltage_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [AB8505_LDO_AUX5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .name = "LDO-AUX5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .id = AB8505_LDO_AUX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .volt_table = ldo_vaux56_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .load_lp_uA = 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* values for CtrlVaux5 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .update_bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .update_reg = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .update_mask = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .update_val = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .update_val_idle = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .update_val_normal = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .voltage_bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .voltage_reg = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .voltage_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) [AB8505_LDO_AUX6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .name = "LDO-AUX6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .id = AB8505_LDO_AUX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .volt_table = ldo_vaux56_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .load_lp_uA = 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* values for CtrlVaux6 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .update_bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .update_reg = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .update_mask = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .update_val = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .update_val_idle = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .update_val_normal = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .voltage_bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .voltage_reg = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .voltage_mask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) [AB8505_LDO_INTCORE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .name = "LDO-INTCORE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .id = AB8505_LDO_INTCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .volt_table = ldo_vintcore_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .load_lp_uA = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .update_reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .update_mask = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .update_val = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .update_val_idle = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .update_val_normal = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .voltage_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .voltage_reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .voltage_mask = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * Fixed Voltage Regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * name, fixed mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * update bank, reg, mask, enable val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) [AB8505_LDO_ADC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .name = "LDO-ADC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .ops = &ab8500_regulator_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .id = AB8505_LDO_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .volt_table = fixed_2000000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .enable_time = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .load_lp_uA = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .update_reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .update_mask = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .update_val = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .update_val_idle = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .update_val_normal = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) [AB8505_LDO_AUDIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .name = "LDO-AUDIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .ops = &ab8500_regulator_volt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .id = AB8505_LDO_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .volt_table = ldo_vaudio_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .update_reg = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .update_mask = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .update_val = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .voltage_bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .voltage_reg = 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .voltage_mask = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) [AB8505_LDO_ANAMIC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .name = "LDO-ANAMIC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .ops = &ab8500_regulator_anamic_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .id = AB8505_LDO_ANAMIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .volt_table = fixed_2050000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .shared_mode = &ldo_anamic1_shared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .update_reg = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .update_mask = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .update_val = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .mode_bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .mode_reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .mode_mask = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .mode_val_idle = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .mode_val_normal = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) [AB8505_LDO_ANAMIC2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .name = "LDO-ANAMIC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .ops = &ab8500_regulator_anamic_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .id = AB8505_LDO_ANAMIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .volt_table = fixed_2050000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .shared_mode = &ldo_anamic2_shared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .update_reg = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .update_mask = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .update_val = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .mode_bank = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .mode_reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .mode_mask = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .mode_val_idle = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .mode_val_normal = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [AB8505_LDO_AUX8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .name = "LDO-AUX8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .ops = &ab8500_regulator_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .id = AB8505_LDO_AUX8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .volt_table = fixed_1800000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .update_bank = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .update_reg = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .update_mask = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .update_val = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * Regulators with fixed voltage and normal/idle modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [AB8505_LDO_ANA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .name = "LDO-ANA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .ops = &ab8500_regulator_volt_mode_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .id = AB8505_LDO_ANA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .volt_table = ldo_vana_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .load_lp_uA = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .update_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .update_reg = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .update_mask = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .update_val = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .update_val_idle = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .update_val_normal = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .voltage_bank = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .voltage_reg = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .voltage_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static struct ab8500_shared_mode ldo_anamic1_shared = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static struct ab8500_shared_mode ldo_anamic2_shared = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct ab8500_reg_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u8 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define REG_INIT(_id, _bank, _addr, _mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .bank = _bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .addr = _addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* AB8500 register init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static struct ab8500_reg_init ab8500_reg_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * 0x30, VanaRequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * 0xc0, VextSupply1RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * 0x03, VextSupply2RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * 0x0c, VextSupply3RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * 0x30, Vaux1RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * 0xc0, Vaux2RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * 0x03, Vaux3RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * 0x04, SwHPReq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * 0x08, VanaSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * 0x20, Vaux1SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * 0x40, Vaux2SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * 0x80, Vaux3SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * 0x10, VextSupply1SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * 0x20, VextSupply2SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * 0x40, VextSupply3SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * 0x08, VanaHwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * 0x20, Vaux1HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * 0x40, Vaux2HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * 0x80, Vaux3HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * 0x01, VextSupply1HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * 0x02, VextSupply2HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * 0x04, VextSupply3HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * 0x08, VanaHwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * 0x20, Vaux1HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * 0x40, Vaux2HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * 0x80, Vaux3HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * 0x01, VextSupply1HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * 0x02, VextSupply2HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * 0x04, VextSupply3HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * 0x20, VanaSwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * 0x80, Vaux1SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * 0x01, Vaux2SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * 0x02, Vaux3SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * 0x04, VextSupply1SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * 0x08, VextSupply2SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * 0x10, VextSupply3SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * 0x02, SysClkReq2Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * 0x04, SysClkReq3Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * 0x08, SysClkReq4Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * 0x10, SysClkReq5Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * 0x20, SysClkReq6Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * 0x40, SysClkReq7Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * 0x80, SysClkReq8Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * 0x02, SysClkReq2Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * 0x04, SysClkReq3Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * 0x08, SysClkReq4Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * 0x10, SysClkReq5Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * 0x20, SysClkReq6Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * 0x40, SysClkReq7Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * 0x80, SysClkReq8Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * 0x02, VTVoutEna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * 0x04, Vintcore12Ena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * 0x38, Vintcore12Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * 0x40, Vintcore12LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * 0x80, VTVoutLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * 0x02, VaudioEna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * 0x04, VdmicEna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * 0x08, Vamic1Ena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * 0x10, Vamic2Ena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * 0x01, Vamic1_dzout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * 0x02, Vamic2_dzout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * 0x03, VpllRegu (NOTE! PRCMU register bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * 0x0c, VanaRegu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * 0x01, VrefDDREna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * 0x02, VrefDDRSleepMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * 0x03, VextSupply1Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * 0x0c, VextSupply2Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * 0x30, VextSupply3Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * 0x40, ExtSupply2Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * 0x80, ExtSupply3Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * 0x03, Vaux1Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * 0x0c, Vaux2Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * 0x03, Vaux3Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * 0x0f, Vaux1Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * 0x0f, Vaux2Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * 0x07, Vaux3Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * 0x01, VextSupply12LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * 0x04, Vaux1Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * 0x08, Vaux2Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * 0x10, Vaux3Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * 0x20, Vintcore12Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * 0x40, VTVoutDisch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * 0x80, VaudioDisch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * 0x02, VanaDisch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * 0x04, VdmicPullDownEna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * 0x10, VdmicDisch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* AB8505 register init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static struct ab8500_reg_init ab8505_reg_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * 0x03, VarmRequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * 0x0c, VsmpsCRequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * 0x30, VsmpsARequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * 0xc0, VsmpsBRequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * 0x03, VsafeRequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * 0x0c, VpllRequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * 0x30, VanaRequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * 0x30, Vaux1RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * 0xc0, Vaux2RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * 0x03, Vaux3RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * 0x04, SwHPReq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * 0x01, VsmpsASysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * 0x02, VsmpsBSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * 0x04, VsafeSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * 0x08, VanaSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * 0x10, VpllSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * 0x20, Vaux1SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * 0x40, Vaux2SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * 0x80, Vaux3SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * 0x01, VsmpsCSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * 0x02, VarmSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * 0x04, VbbSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * 0x08, VsmpsMSysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * 0x01, VsmpsAHwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * 0x02, VsmpsBHwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * 0x04, VsafeHwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * 0x08, VanaHwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * 0x10, VpllHwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * 0x20, Vaux1HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * 0x40, Vaux2HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * 0x80, Vaux3HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * 0x08, VsmpsMHwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * 0x01, VsmpsAHwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * 0x02, VsmpsBHwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * 0x04, VsafeHwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * 0x08, VanaHwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * 0x10, VpllHwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * 0x20, Vaux1HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * 0x40, Vaux2HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * 0x80, Vaux3HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * 0x08, VsmpsMHwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * 0x01, VsmpsCSwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * 0x02, VarmSwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * 0x04, VsmpsASwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * 0x08, VsmpsBSwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * 0x10, VsafeSwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * 0x20, VanaSwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * 0x40, VpllSwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * 0x80, Vaux1SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * 0x01, Vaux2SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * 0x02, Vaux3SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * 0x20, VsmpsMSwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * 0x02, SysClkReq2Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * 0x04, SysClkReq3Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * 0x08, SysClkReq4Valid1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * 0x02, SysClkReq2Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * 0x04, SysClkReq3Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * 0x08, SysClkReq4Valid2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * 0x01, Vaux4SwHPReqValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * 0x02, Vaux4HwHPReq2Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * 0x04, Vaux4HwHPReq1Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * 0x08, Vaux4SysClkReq1HPValid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * 0x02, VadcEna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * 0x04, VintCore12Ena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * 0x38, VintCore12Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * 0x40, VintCore12LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * 0x80, VadcLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * 0x02, VaudioEna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * 0x04, VdmicEna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * 0x08, Vamic1Ena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * 0x10, Vamic2Ena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * 0x01, Vamic1_dzout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * 0x02, Vamic2_dzout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * 0x03, VsmpsARegu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * 0x0c, VsmpsASelCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * 0x10, VsmpsAAutoMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * 0x20, VsmpsAPWMMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * 0x03, VsmpsBRegu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * 0x0c, VsmpsBSelCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * 0x10, VsmpsBAutoMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * 0x20, VsmpsBPWMMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * 0x03, VsafeRegu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * 0x0c, VsafeSelCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * 0x10, VsafeAutoMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * 0x20, VsafePWMMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * 0x03, VpllRegu (NOTE! PRCMU register bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * 0x0c, VanaRegu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * 0x03, VextSupply1Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * 0x0c, VextSupply2Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * 0x30, VextSupply3Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * 0x40, ExtSupply2Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * 0x80, ExtSupply3Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * 0x03, Vaux1Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * 0x0c, Vaux2Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * 0x0f, Vaux3Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * 0x3f, VsmpsASel1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * 0x3f, VsmpsASel2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * 0x3f, VsmpsASel3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * 0x3f, VsmpsBSel1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * 0x3f, VsmpsBSel2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * 0x3f, VsmpsBSel3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * 0x7f, VsafeSel1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * 0x3f, VsafeSel2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * 0x3f, VsafeSel3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * 0x0f, Vaux1Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * 0x0f, Vaux2Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * 0x07, Vaux3Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * 0x30, VRF1Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * 0x03, Vaux4RequestCtrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * 0x03, Vaux4Regu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * 0x0f, Vaux4Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * 0x04, Vaux1Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * 0x08, Vaux2Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * 0x10, Vaux3Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * 0x20, Vintcore12Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * 0x40, VTVoutDisch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * 0x80, VaudioDisch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * 0x02, VanaDisch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * 0x04, VdmicPullDownEna
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * 0x10, VdmicDisch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * 0x01, Vaux4Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * 0x07, Vaux5Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * 0x08, Vaux5LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) * 0x10, Vaux5Ena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * 0x20, Vaux5Disch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) * 0x40, Vaux5DisSfst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * 0x80, Vaux5DisPulld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * 0x07, Vaux6Sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * 0x08, Vaux6LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * 0x10, Vaux6Ena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * 0x80, Vaux6DisPulld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static struct of_regulator_match ab8500_regulator_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static struct of_regulator_match ab8505_regulator_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct ab8500_regulator_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) int info_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct ab8500_reg_init *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int init_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct of_regulator_match *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) int match_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) } abx500_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static void abx500_get_regulator_info(struct ab8500 *ab8500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (is_ab8505(ab8500)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) abx500_regulator.info = ab8505_regulator_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) abx500_regulator.init = ab8505_reg_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) abx500_regulator.match = ab8505_regulator_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) abx500_regulator.info = ab8500_regulator_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) abx500_regulator.init = ab8500_reg_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) abx500_regulator.match = ab8500_regulator_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static int ab8500_regulator_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct regulator_init_data *init_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) int id, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct ab8500_regulator_info *info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* assign per-regulator data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) info = &abx500_regulator.info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) config.init_data = init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) config.driver_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) config.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /* fix for hardware before ab8500v2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (is_ab8500_1p1_or_earlier(ab8500)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (info->desc.id == AB8500_LDO_AUX3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) info->desc.n_voltages =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ARRAY_SIZE(ldo_vauxn_voltages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) info->desc.volt_table = ldo_vauxn_voltages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) info->voltage_mask = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /* register regulator with framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) rdev = devm_regulator_register(&pdev->dev, &info->desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev_err(&pdev->dev, "failed to register regulator %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) info->desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static int ab8500_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct of_regulator_match *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (!ab8500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dev_err(&pdev->dev, "null mfd parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) abx500_get_regulator_info(ab8500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) err = of_regulator_match(&pdev->dev, np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) abx500_regulator.match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) abx500_regulator.match_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) "Error parsing regulator init data: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) match = abx500_regulator.match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) for (i = 0; i < abx500_regulator.info_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) err = ab8500_regulator_register(pdev, match[i].init_data, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) match[i].of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static struct platform_driver ab8500_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .probe = ab8500_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .name = "ab8500-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static int __init ab8500_regulator_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) ret = platform_driver_register(&ab8500_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pr_err("Failed to register ab8500 regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) subsys_initcall(ab8500_regulator_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static void __exit ab8500_regulator_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) platform_driver_unregister(&ab8500_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) module_exit(ab8500_regulator_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) MODULE_ALIAS("platform:ab8500-regulator");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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