^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IDT RXS Gen.3 Serial RapidIO switch family support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Integrated Device Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/rio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rio_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/rio_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../rio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RIO_EM_PW_STAT 0x40020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RIO_PW_CTL 0x40204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RIO_PW_CTL_PW_TMR 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RIO_PW_ROUTE 0x40208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RIO_EM_DEV_INT_EN 0x40030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RIO_BC_L2_Gn_ENTRYx_CSR(n, x) (0x31000 + (n)*0x400 + (x)*0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RIO_SPx_L2_Gn_ENTRYy_CSR(x, n, y) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (0x51000 + (x)*0x2000 + (n)*0x400 + (y)*0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) idtg3_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u16 table, u16 route_destid, u8 route_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 entry = route_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pr_debug("RIO: %s t=0x%x did_%x to p_%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __func__, table, route_destid, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (route_destid > 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (route_port == RIO_INVALID_ROUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) entry = RIO_RT_ENTRY_DROP_PKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (table == RIO_GLOBAL_TABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Use broadcast register to update all per-port tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) err = rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RIO_BC_L2_Gn_ENTRYx_CSR(0, route_destid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Verify that specified port/table number is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) err = rio_mport_read_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) RIO_SWP_INFO_CAR, &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (table >= RIO_GET_TOTAL_PORTS(rval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) err = rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RIO_SPx_L2_Gn_ENTRYy_CSR(table, 0, route_destid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) idtg3_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u16 table, u16 route_destid, u8 *route_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (route_destid > 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) err = rio_mport_read_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RIO_SWP_INFO_CAR, &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * This switch device does not have the dedicated global routing table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * It is substituted by reading routing table of the ingress port of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * maintenance read requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (table == RIO_GLOBAL_TABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) table = RIO_GET_PORT_NUM(rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else if (table >= RIO_GET_TOTAL_PORTS(rval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) err = rio_mport_read_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) RIO_SPx_L2_Gn_ENTRYy_CSR(table, 0, route_destid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (rval == RIO_RT_ENTRY_DROP_PKT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *route_port = RIO_INVALID_ROUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *route_port = (u8)rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) idtg3_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (table == RIO_GLOBAL_TABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) for (i = 0; i <= 0xff; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) err = rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) RIO_BC_L2_Gn_ENTRYx_CSR(0, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) RIO_RT_ENTRY_DROP_PKT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err = rio_mport_read_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) RIO_SWP_INFO_CAR, &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (table >= RIO_GET_TOTAL_PORTS(rval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i <= 0xff; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) err = rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) RIO_SPx_L2_Gn_ENTRYy_CSR(table, 0, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) RIO_RT_ENTRY_DROP_PKT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * This routine performs device-specific initialization only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * All standard EM configuration should be performed at upper level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) idtg3_em_init(struct rio_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int i, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Disable assertion of interrupt signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) rio_write_config_32(rdev, RIO_EM_DEV_INT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Disable port-write event notifications during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RIO_EM_PW_TX_CTRL_PW_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Configure Port-Write notifications for hot-swap events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for (i = 0; i < tmp; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rio_read_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RIO_DEV_PORT_N_ERR_STS_CSR(rdev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (rval & RIO_PORT_N_ERR_STS_PORT_UA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Clear events signaled before enabling notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rio_write_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rdev->em_efptr + RIO_EM_PN_ERR_DETECT(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Enable event notifications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rio_write_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rdev->em_efptr + RIO_EM_PN_ERRRATE_EN(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) RIO_EM_PN_ERRRATE_EN_OK2U | RIO_EM_PN_ERRRATE_EN_U2OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Enable port-write generation on events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rio_write_config_32(rdev, RIO_PLM_SPx_PW_EN(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) RIO_PLM_SPx_PW_EN_OK2U | RIO_PLM_SPx_PW_EN_LINIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Set Port-Write destination port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tmp = RIO_GET_PORT_NUM(rdev->swpinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rio_write_config_32(rdev, RIO_PW_ROUTE, 1 << tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Enable sending port-write event notifications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* set TVAL = ~50us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rio_write_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * idtg3_em_handler - device-specific error handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * If the link is down (PORT_UNINIT) does nothing - this is considered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * as link partner removal from the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * If the link is up (PORT_OK) - situation is handled as *new* device insertion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * In this case ERR_STOP bits are cleared by issuing soft reset command to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * reporting port. Inbound and outbound ackIDs are cleared by the reset as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * This way the port is synchronized with freshly inserted device (assuming it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * was reset/powered-up on insertion).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * TODO: This is not sufficient in a situation when a link between two devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * was down and up again (e.g. cable disconnect). For that situation full ackID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * realignment process has to be implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) idtg3_em_handler(struct rio_dev *rdev, u8 pnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) rio_read_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) RIO_DEV_PORT_N_ERR_STS_CSR(rdev, pnum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) &err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Do nothing for device/link removal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (err_status & RIO_PORT_N_ERR_STS_PORT_UNINIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* When link is OK we have a device insertion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Request port soft reset to clear errors if they present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Inbound and outbound ackIDs will be 0 after reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (err_status & (RIO_PORT_N_ERR_STS_OUT_ES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) RIO_PORT_N_ERR_STS_INP_ES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rio_read_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum), &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rio_write_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rval | RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rio_write_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum), rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct rio_switch_ops idtg3_switch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .add_entry = idtg3_route_add_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .get_entry = idtg3_route_get_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .clr_table = idtg3_route_clr_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .em_init = idtg3_em_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .em_handle = idtg3_em_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int idtg3_probe(struct rio_dev *rdev, const struct rio_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_lock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (rdev->rswitch->ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_unlock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) rdev->rswitch->ops = &idtg3_switch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (rdev->do_enum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Disable hierarchical routing support: Existing fabric
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * enumeration/discovery process (see rio-scan.c) uses 8-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * flat destination ID routing only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) rio_write_config_32(rdev, 0x5000 + RIO_BC_RT_CTL_CSR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spin_unlock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void idtg3_remove(struct rio_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_lock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (rdev->rswitch->ops == &idtg3_switch_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) rdev->rswitch->ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_unlock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Gen3 switches repeat sending PW messages until a corresponding event flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * is cleared. Use shutdown notification to disable generation of port-write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * messages if their destination node is shut down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void idtg3_shutdown(struct rio_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u16 destid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Currently the enumerator node acts also as PW handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!rdev->do_enum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pr_debug("RIO: %s(%s)\n", __func__, rio_name(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rio_read_config_32(rdev, RIO_PW_ROUTE, &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) i = RIO_GET_PORT_NUM(rdev->swpinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Check port-write destination port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!((1 << i) & rval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Disable sending port-write event notifications if PW destID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * matches to one of the enumerator node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TGT_DEVID, &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (rval & RIO_EM_PW_TGT_DEVID_DEV16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) destid = rval >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) destid = ((rval & RIO_EM_PW_TGT_DEVID_D8) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (rdev->net->hport->host_deviceid == destid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) rio_write_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) rdev->em_efptr + RIO_EM_PW_TX_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pr_debug("RIO: %s(%s) PW transmission disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __func__, rio_name(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct rio_device_id idtg3_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {RIO_DEVICE(RIO_DID_IDTRXS1632, RIO_VID_IDT)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {RIO_DEVICE(RIO_DID_IDTRXS2448, RIO_VID_IDT)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 0, } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct rio_driver idtg3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .name = "idt_gen3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .id_table = idtg3_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .probe = idtg3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .remove = idtg3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .shutdown = idtg3_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int __init idtg3_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return rio_register_driver(&idtg3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void __exit idtg3_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pr_debug("RIO: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) rio_unregister_driver(&idtg3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pr_debug("RIO: %s done\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) device_initcall(idtg3_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) module_exit(idtg3_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_DESCRIPTION("IDT RXS Gen.3 Serial RapidIO switch family driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_AUTHOR("Integrated Device Technology, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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