Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * IDT CPS Gen.2 Serial RapidIO switch family support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2010 Integrated Device Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Alexandre Bounine <alexandre.bounine@idt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/rio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/rio_drv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/rio_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "../rio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LOCAL_RTE_CONF_DESTID_SEL	0x010070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LOCAL_RTE_CONF_DESTID_SEL_PSEL	0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IDT_LT_ERR_REPORT_EN	0x03100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IDT_PORT_ERR_REPORT_EN(n)	(0x031044 + (n)*0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IDT_PORT_ERR_REPORT_EN_BC	0x03ff04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IDT_PORT_ISERR_REPORT_EN(n)	(0x03104C + (n)*0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IDT_PORT_ISERR_REPORT_EN_BC	0x03ff0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IDT_PORT_INIT_TX_ACQUIRED	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IDT_LANE_ERR_REPORT_EN(n)	(0x038010 + (n)*0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IDT_LANE_ERR_REPORT_EN_BC	0x03ff10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IDT_DEV_CTRL_1		0xf2000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IDT_DEV_CTRL_1_GENPW		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IDT_DEV_CTRL_1_PRSTBEH		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IDT_CFGBLK_ERR_CAPTURE_EN	0x020008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IDT_CFGBLK_ERR_REPORT		0xf20014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IDT_CFGBLK_ERR_REPORT_GENPW		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IDT_AUX_PORT_ERR_CAP_EN	0x020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IDT_AUX_ERR_REPORT_EN	0xf20018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IDT_AUX_PORT_ERR_LOG_I2C	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IDT_AUX_PORT_ERR_LOG_JTAG	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define	IDT_ISLTL_ADDRESS_CAP	0x021014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IDT_RIO_DOMAIN		0xf20020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IDT_RIO_DOMAIN_MASK		0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IDT_PW_INFO_CSR		0xf20024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IDT_SOFT_RESET		0xf20040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IDT_SOFT_RESET_REQ		0x00030097
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IDT_I2C_MCTRL		0xf20050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IDT_I2C_MCTRL_GENPW		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IDT_JTAG_CTRL		0xf2005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IDT_JTAG_CTRL_GENPW		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IDT_LANE_CTRL(n)	(0xff8000 + (n)*0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IDT_LANE_CTRL_BC	0xffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IDT_LANE_CTRL_GENPW		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IDT_LANE_DFE_1_BC	0xffff18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IDT_LANE_DFE_2_BC	0xffff1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IDT_PORT_OPS(n)		(0xf40004 + (n)*0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IDT_PORT_OPS_GENPW		0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IDT_PORT_OPS_PL_ELOG		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IDT_PORT_OPS_LL_ELOG		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IDT_PORT_OPS_LT_ELOG		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IDT_PORT_OPS_BC		0xf4ff04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IDT_PORT_ISERR_DET(n)	(0xf40008 + (n)*0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IDT_ERR_CAP		0xfd0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IDT_ERR_CAP_LOG_OVERWR		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IDT_ERR_RD		0xfd0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IDT_DEFAULT_ROUTE	0xde
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IDT_NO_ROUTE		0xdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		       u16 table, u16 route_destid, u8 route_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * Select routing table to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (table == RIO_GLOBAL_TABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		table = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		table++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (route_port == RIO_INVALID_ROUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		route_port = IDT_DEFAULT_ROUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				  LOCAL_RTE_CONF_DESTID_SEL, table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * Program destination port for the specified destID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				  RIO_STD_RTE_CONF_DESTID_SEL_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				  (u32)route_destid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				  RIO_STD_RTE_CONF_PORT_SEL_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				  (u32)route_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		       u16 table, u16 route_destid, u8 *route_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * Select routing table to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (table == RIO_GLOBAL_TABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		table = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		table++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				  LOCAL_RTE_CONF_DESTID_SEL, table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				  RIO_STD_RTE_CONF_DESTID_SEL_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				  route_destid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	rio_mport_read_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				 RIO_STD_RTE_CONF_PORT_SEL_CSR, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (IDT_DEFAULT_ROUTE == (u8)result || IDT_NO_ROUTE == (u8)result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		*route_port = RIO_INVALID_ROUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		*route_port = (u8)result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		       u16 table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * Select routing table to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (table == RIO_GLOBAL_TABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		table = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		table++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				  LOCAL_RTE_CONF_DESTID_SEL, table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	for (i = RIO_STD_RTE_CONF_EXTCFGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	     i <= (RIO_STD_RTE_CONF_EXTCFGEN | 0xff);) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			RIO_STD_RTE_CONF_DESTID_SEL_CSR, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			RIO_STD_RTE_CONF_PORT_SEL_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			(IDT_DEFAULT_ROUTE << 24) | (IDT_DEFAULT_ROUTE << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			(IDT_DEFAULT_ROUTE << 8) | IDT_DEFAULT_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		       u8 sw_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 * Switch domain configuration operates only at global level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	rio_mport_write_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				  IDT_RIO_DOMAIN, (u32)sw_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		       u8 *sw_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * Switch domain configuration operates only at global level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	rio_mport_read_config_32(mport, destid, hopcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				IDT_RIO_DOMAIN, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	*sw_domain = (u8)(regval & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) idtg2_em_init(struct rio_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int i, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * This routine performs device-specific initialization only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * All standard EM configuration should be performed at upper level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Set Port-Write info CSR: PRIO=3 and CRF=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * Configure LT LAYER error reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* Enable standard (RIO.p8) error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			REM_LTL_ERR_UNSUPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* Use Port-Writes for LT layer error reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * Enable per-port reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	rio_write_config_32(rdev, IDT_DEV_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * Configure PORT error reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* Report all RIO.p8 errors supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Configure reporting of implementation specific errors/events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			    IDT_PORT_INIT_TX_ACQUIRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Use Port-Writes for port error reporting and enable error logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = 0; i < tmp; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		rio_write_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				IDT_PORT_OPS_PL_ELOG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				IDT_PORT_OPS_LL_ELOG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				IDT_PORT_OPS_LT_ELOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* Overwrite error log if full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 * Configure LANE error reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* Disable line error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Use Port-Writes for lane error reporting (when enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 * (do per-lane update because lanes may have different configuration)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	for (i = 0; i < tmp; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		rio_write_config_32(rdev, IDT_LANE_CTRL(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				    regval | IDT_LANE_CTRL_GENPW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	 * Configure AUX error reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	/* Disable JTAG and I2C Error capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/* Disable JTAG and I2C Error reporting/logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* Disable Port-Write notification from JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	rio_write_config_32(rdev, IDT_JTAG_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/* Disable Port-Write notification from I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	rio_read_config_32(rdev, IDT_I2C_MCTRL, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 * Configure CFG_BLK error reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* Disable Configuration Block error capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	/* Disable Port-Writes for Configuration Block error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			    regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* set TVAL = ~50us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	rio_write_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	u32 regval, em_perrdet, em_ltlerrdet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	rio_read_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (em_ltlerrdet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		/* Service Logical/Transport Layer Error(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			/* Implementation specific error reported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			rio_read_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 					IDT_ISLTL_ADDRESS_CAP, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			pr_debug("RIO: %s Implementation Specific LTL errors" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 				 " 0x%x @(0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				 rio_name(rdev), em_ltlerrdet, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			/* Clear implementation specific address capture CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	rio_read_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (em_perrdet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		/* Service Port-Level Error(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		if (em_perrdet & REM_PED_IMPL_SPEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			/* Implementation Specific port error reported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			/* Get IS errors reported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			rio_read_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 					IDT_PORT_ISERR_DET(portnum), &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			pr_debug("RIO: %s Implementation Specific Port" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				 " errors 0x%x\n", rio_name(rdev), regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			/* Clear all implementation specific events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			rio_write_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 					IDT_PORT_ISERR_DET(portnum), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	struct rio_dev *rdev = to_rio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	ssize_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	while (!rio_read_config_32(rdev, IDT_ERR_RD, &regval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		if (!regval)    /* 0 = end of log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		len += snprintf(buf + len, PAGE_SIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 					"%08x\n", regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		if (len >= (PAGE_SIZE - 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int idtg2_sysfs(struct rio_dev *rdev, bool create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	struct device *dev = &rdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	if (create) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		/* Initialize sysfs entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		err = device_create_file(dev, &dev_attr_errlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 			dev_err(dev, "Unable create sysfs errlog file\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		device_remove_file(dev, &dev_attr_errlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct rio_switch_ops idtg2_switch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.add_entry = idtg2_route_add_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.get_entry = idtg2_route_get_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.clr_table = idtg2_route_clr_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.set_domain = idtg2_set_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.get_domain = idtg2_get_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.em_init = idtg2_em_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.em_handle = idtg2_em_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int idtg2_probe(struct rio_dev *rdev, const struct rio_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	spin_lock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	if (rdev->rswitch->ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		spin_unlock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	rdev->rswitch->ops = &idtg2_switch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (rdev->do_enum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		/* Ensure that default routing is disabled on startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		rio_write_config_32(rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 				    RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	spin_unlock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	/* Create device-specific sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	idtg2_sysfs(rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void idtg2_remove(struct rio_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	spin_lock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	if (rdev->rswitch->ops != &idtg2_switch_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		spin_unlock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	rdev->rswitch->ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	spin_unlock(&rdev->rswitch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	/* Remove device-specific sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	idtg2_sysfs(rdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const struct rio_device_id idtg2_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	{RIO_DEVICE(RIO_DID_IDTCPS1848, RIO_VID_IDT)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	{RIO_DEVICE(RIO_DID_IDTCPS1616, RIO_VID_IDT)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	{RIO_DEVICE(RIO_DID_IDTVPS1616, RIO_VID_IDT)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	{RIO_DEVICE(RIO_DID_IDTSPS1616, RIO_VID_IDT)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	{RIO_DEVICE(RIO_DID_IDTCPS1432, RIO_VID_IDT)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	{ 0, }	/* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct rio_driver idtg2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	.name = "idt_gen2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.id_table = idtg2_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	.probe = idtg2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.remove = idtg2_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int __init idtg2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	return rio_register_driver(&idtg2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void __exit idtg2_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	pr_debug("RIO: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	rio_unregister_driver(&idtg2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	pr_debug("RIO: %s done\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) device_initcall(idtg2_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) module_exit(idtg2_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MODULE_DESCRIPTION("IDT CPS Gen.2 Serial RapidIO switch family driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MODULE_AUTHOR("Integrated Device Technology, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MODULE_LICENSE("GPL");