^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Tsi721 PCIExpress-to-SRIO bridge definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011, Integrated Device Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __TSI721_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __TSI721_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Debug output filtering masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) DBG_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) DBG_INIT = BIT(0), /* driver init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) DBG_EXIT = BIT(1), /* driver exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) DBG_MPORT = BIT(2), /* mport add/remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) DBG_MAINT = BIT(3), /* maintenance ops messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) DBG_DMA = BIT(4), /* DMA transfer messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DBG_DMAV = BIT(5), /* verbose DMA transfer messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DBG_IBW = BIT(6), /* inbound window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DBG_EVENT = BIT(7), /* event handling messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DBG_OBW = BIT(8), /* outbound window messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DBG_DBELL = BIT(9), /* doorbell messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DBG_OMSG = BIT(10), /* doorbell messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DBG_IMSG = BIT(11), /* doorbell messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DBG_ALL = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern u32 tsi_dbg_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define tsi_debug(level, dev, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (DBG_##level & tsi_dbg_level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) dev_dbg(dev, "%s: " fmt "\n", __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define tsi_debug(level, dev, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) no_printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define tsi_info(dev, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) dev_info(dev, "%s: " fmt "\n", __func__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define tsi_warn(dev, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dev_warn(dev, "%s: WARNING " fmt "\n", __func__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define tsi_err(dev, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dev_err(dev, "%s: ERROR " fmt "\n", __func__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRV_NAME "tsi721"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DEFAULT_HOPCOUNT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DEFAULT_DESTID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* PCI device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCI_DEVICE_ID_TSI721 0x80ab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BAR_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BAR_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BAR_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BAR_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TSI721_PC2SR_BARS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TSI721_PC2SR_WINS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TSI721_PC2SR_ZONES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IDB_QSIZE 512 /* Inbound Doorbell Queue size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Memory space sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TSI721_REG_SPACE_SIZE (512 * 1024) /* 512K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TSI721_DB_WIN_SIZE (16 * 1024 * 1024) /* 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RIO_TT_CODE_8 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RIO_TT_CODE_16 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TSI721_DMA_MAXCH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TSI721_DMA_MINSTSSZ 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TSI721_DMA_STSBLKSZ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TSI721_SRIO_MAXCH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DBELL_SID(buf) (((u8)buf[2] << 8) | (u8)buf[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DBELL_TID(buf) (((u8)buf[4] << 8) | (u8)buf[5])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TSI721_RIO_PW_MSG_SIZE 16 /* Tsi721 saves only 16 bytes of PW msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Registers in PCIe configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TSI721_PCIECFG_MSIXTBL 0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TSI721_MSIXTBL_OFFSET 0x2c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TSI721_PCIECFG_MSIXPBA 0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TSI721_MSIXPBA_OFFSET 0x2a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TSI721_PCIECFG_EPCTL 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Event Management Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TSI721_RIO_EM_INT_STAT 0x10910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TSI721_RIO_EM_INT_ENABLE 0x10914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TSI721_RIO_EM_DEV_INT_EN 0x10930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Port-Write Block Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TSI721_RIO_PW_CTL 0x10a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TSI721_RIO_PW_CTL_PWT_103 (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TSI721_RIO_PW_CTL_PWT_205 (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TSI721_RIO_PW_CTL_PWT_410 (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TSI721_RIO_PW_CTL_PWT_820 (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TSI721_RIO_PW_CTL_PWC_REL 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TSI721_RIO_PW_RX_STAT 0x10a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Inbound Doorbells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TSI721_IDB_ENTRY_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TSI721_IDQ_SUSPEND 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TSI721_IDQ_INIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TSI721_IDQ_RUN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TSI721_IDQ_MASK_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TSI721_IDQ_MASK_PATT 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TSI721_IDQ_RP_PTR 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TSI721_IDQ_WP_PTR 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TSI721_IDQ_BASEL_ADDR 0xffffffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TSI721_IDQ_SIZE_MIN 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TSI721_IDQ_SIZE_MAX (512 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TSI721_SR_CHINT_ODBOK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TSI721_SR_CHINT_IDBQRCV 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TSI721_SR_CHINT_SUSP 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TSI721_SR_CHINT_ODBTO 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TSI721_SR_CHINT_ODBRTRY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TSI721_SR_CHINT_ODBERR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TSI721_SR_CHINT_ALL 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TSI721_IBWIN_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TSI721_IBWIN_LB(x) (0x29000 + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TSI721_IBWIN_LB_BA 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TSI721_IBWIN_LB_WEN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TSI721_IBWIN_UB(x) (0x29004 + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TSI721_IBWIN_SZ(x) (0x29008 + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TSI721_IBWIN_SZ_SIZE 0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TSI721_IBWIN_SIZE(size) (__fls(size) - 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TSI721_IBWIN_TLA(x) (0x2900c + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TSI721_IBWIN_TLA_ADD 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TSI721_IBWIN_TUA(x) (0x29010 + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TSI721_SR2PC_GEN_INTE 0x29800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TSI721_SR2PC_PWE 0x29804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TSI721_SR2PC_GEN_INT 0x29808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TSI721_DEV_INTE 0x29840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TSI721_DEV_INT 0x29844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TSI721_DEV_INTSET 0x29848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TSI721_DEV_INT_BDMA_CH 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TSI721_DEV_INT_BDMA_NCH 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TSI721_DEV_INT_SMSG_CH 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TSI721_DEV_INT_SMSG_NCH 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TSI721_DEV_INT_SR2PC_CH 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TSI721_DEV_INT_SRIO 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TSI721_DEV_CHAN_INTE 0x2984c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TSI721_DEV_CHAN_INT 0x29850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TSI721_INT_SR2PC_CHAN_M 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TSI721_INT_SR2PC_CHAN(x) (1 << (24 + (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TSI721_INT_IMSG_CHAN_M 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TSI721_INT_OMSG_CHAN_M 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TSI721_INT_BDMA_CHAN_M 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TSI721_INT_BDMA_CHAN(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * PC2SR block registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TSI721_OBWIN_NUM TSI721_PC2SR_WINS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TSI721_OBWINLB_BA 0xffff8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TSI721_OBWINLB_WEN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TSI721_OBWINSZ_SIZE 0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TSI721_ZONE_SEL 0x41300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TSI721_ZONE_SEL_RD_WRB 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TSI721_ZONE_SEL_GO 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TSI721_ZONE_SEL_WIN 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TSI721_ZONE_SEL_ZONE 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TSI721_LUT_DATA0 0x41304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TSI721_LUT_DATA0_ADD 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TSI721_LUT_DATA0_RDTYPE 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TSI721_LUT_DATA0_NREAD 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TSI721_LUT_DATA0_MNTRD 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TSI721_LUT_DATA0_RDCRF 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TSI721_LUT_DATA0_WRCRF 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TSI721_LUT_DATA0_WRTYPE 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TSI721_LUT_DATA0_NWR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TSI721_LUT_DATA0_MNTWR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TSI721_LUT_DATA0_NWR_R 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TSI721_LUT_DATA1 0x41308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TSI721_LUT_DATA2 0x4130c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TSI721_LUT_DATA2_HC 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TSI721_LUT_DATA2_ADD65 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TSI721_LUT_DATA2_TT 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TSI721_LUT_DATA2_DSTID 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TSI721_PC2SR_INTE 0x41310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TSI721_DEVCTL 0x48004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TSI721_I2C_INT_ENABLE 0x49120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Block DMA Engine Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * x = 0..7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TSI721_DMAC_DWRCNT 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TSI721_DMAC_DRDCNT 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TSI721_DMAC_CTL 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TSI721_DMAC_CTL_SUSP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TSI721_DMAC_CTL_INIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TSI721_DMAC_INT 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TSI721_DMAC_INT_STFULL 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TSI721_DMAC_INT_DONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TSI721_DMAC_INT_SUSP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TSI721_DMAC_INT_ERR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TSI721_DMAC_INT_IOFDONE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TSI721_DMAC_INT_ALL 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TSI721_DMAC_INTSET 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TSI721_DMAC_STS 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TSI721_DMAC_STS_ABORT 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TSI721_DMAC_STS_RUN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TSI721_DMAC_STS_CS 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TSI721_DMAC_INTE 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TSI721_DMAC_DPTRL 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TSI721_DMAC_DPTRL_MASK 0xffffffe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TSI721_DMAC_DPTRH 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TSI721_DMAC_DSBL 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TSI721_DMAC_DSBL_MASK 0xffffffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TSI721_DMAC_DSBH 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TSI721_DMAC_DSSZ 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TSI721_DMAC_DSRP 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TSI721_DMAC_DSRP_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TSI721_DMAC_DSWP 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TSI721_DMAC_DSWP_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TSI721_BDMA_INTE 0x5f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Messaging definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TSI721_MSG_BUFFER_SIZE RIO_MAX_MSG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TSI721_MSG_MAX_SIZE RIO_MAX_MSG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TSI721_IMSG_MAXCH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TSI721_IMSG_CHNUM TSI721_IMSG_MAXCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TSI721_IMSGD_MIN_RING_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TSI721_IMSGD_RING_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TSI721_OMSG_CHNUM 4 /* One channel per MBOX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TSI721_OMSGD_MIN_RING_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TSI721_OMSGD_RING_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Outbound Messaging Engine Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * x = 0..7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TSI721_OBDMAC_CTL_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TSI721_OBDMAC_CTL_SUSPEND 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TSI721_OBDMAC_CTL_INIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TSI721_OBDMAC_INT_MASK 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define TSI721_OBDMAC_INT_ST_FULL 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define TSI721_OBDMAC_INT_DONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TSI721_OBDMAC_INT_SUSPENDED 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TSI721_OBDMAC_INT_ERROR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TSI721_OBDMAC_INT_IOF_DONE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TSI721_OBDMAC_INT_ALL TSI721_OBDMAC_INT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TSI721_OBDMAC_STS_MASK 0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TSI721_OBDMAC_STS_ABORT 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TSI721_OBDMAC_STS_RUN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TSI721_OBDMAC_STS_CS 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TSI721_OBDMAC_PWE_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TSI721_OBDMAC_DPTRH_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define TSI721_OBDMAC_DSBL_MASK 0xffffffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define TSI721_OBDMAC_DSBH_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TSI721_OBDMAC_DSSZ_MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define TSI721_OBDMAC_DSRP_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define TSI721_OBDMAC_DSWP_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TSI721_RQRPTO 0x60010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define TSI721_RQRPTO_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TSI721_RQRPTO_VAL 400 /* Response TO value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Inbound Messaging Engine Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * x = 0..7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TSI721_IB_DEVID_GLOBAL 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TSI721_IBDMAC_FQBL_MASK 0xffffffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define TSI721_IBDMAC_FQBH_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TSI721_IBDMAC_FQSZ_ENTRY_INX TSI721_IMSGD_RING_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define TSI721_IBDMAC_FQSZ_MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define TSI721_IBDMAC_FQRP_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define TSI721_IBDMAC_FQWP_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define TSI721_IBDMAC_FQTH_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define TSI721_IB_DEVID 0x60020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define TSI721_IB_DEVID_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define TSI721_IBDMAC_CTL_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define TSI721_IBDMAC_CTL_SUSPEND 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define TSI721_IBDMAC_CTL_INIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define TSI721_IBDMAC_STS_MASK 0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define TSI721_IBSMAC_STS_ABORT 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define TSI721_IBSMAC_STS_RUN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define TSI721_IBSMAC_STS_CS 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define TSI721_IBDMAC_INT_MASK 0x0000100f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define TSI721_IBDMAC_INT_SRTO 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define TSI721_IBDMAC_INT_SUSPENDED 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define TSI721_IBDMAC_INT_PC_ERROR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define TSI721_IBDMAC_INT_FQ_LOW 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define TSI721_IBDMAC_INT_DQ_RCV 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define TSI721_IBDMAC_INT_ALL TSI721_IBDMAC_INT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TSI721_IBDMAC_PWE_MASK 0x00001700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define TSI721_IBDMAC_PWE_SRTO 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TSI721_IBDMAC_PWE_IMP_SP 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define TSI721_IBDMAC_DQBL_MASK 0xffffffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define TSI721_IBDMAC_DQBH_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define TSI721_IBDMAC_DQRP_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define TSI721_IBDMAC_DQWR_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define TSI721_IBDMAC_DQSZ_MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Messaging Engine Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define TSI721_SMSG_PWE 0x6a004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define TSI721_SMSG_INTE 0x6a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define TSI721_SMSG_INT 0x6a008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define TSI721_SMSG_INTSET 0x6a010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define TSI721_SMSG_INT_MASK 0x0086ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define TSI721_SMSG_INT_UNS_RSP 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define TSI721_SMSG_INT_ECC_NCOR 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define TSI721_SMSG_INT_ECC_COR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define TSI721_SMSG_ECC_LOG 0x6a014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define TSI721_SMSG_ECC_LOG_MASK 0x00070007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define TSI721_RETRY_GEN_CNT 0x6a100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define TSI721_RETRY_GEN_CNT_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define TSI721_RETRY_RX_CNT 0x6a104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define TSI721_RETRY_RX_CNT_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Block DMA Descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct tsi721_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __le32 type_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define TSI721_DMAD_DEVID 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define TSI721_DMAD_CRF 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define TSI721_DMAD_PRIO 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define TSI721_DMAD_RTYPE 0x00780000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define TSI721_DMAD_IOF 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define TSI721_DMAD_DTYPE 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) __le32 bcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define TSI721_DMAD_TT 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define TSI721_DMAD_RADDR0 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __le32 raddr_lo; /* if DTYPE == (1 || 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) __le32 next_lo; /* if DTYPE == 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define TSI721_DMAD_CFGOFF 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define TSI721_DMAD_HOPCNT 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) __le32 raddr_hi; /* if DTYPE == (1 || 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) __le32 next_hi; /* if DTYPE == 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct { /* if DTYPE == 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __le32 bufptr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __le32 bufptr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) __le32 s_dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __le32 s_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __le32 data[4]; /* if DTYPE == 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 reserved[4]; /* if DTYPE == 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) } __aligned(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Inbound Messaging Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct tsi721_imsg_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) __le32 type_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define TSI721_IMD_DEVID 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define TSI721_IMD_CRF 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define TSI721_IMD_PRIO 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define TSI721_IMD_TT 0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define TSI721_IMD_DTYPE 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) __le32 msg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define TSI721_IMD_BCOUNT 0x00000ff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define TSI721_IMD_SSIZE 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define TSI721_IMD_LETER 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define TSI721_IMD_XMBOX 0x003c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define TSI721_IMD_MBOX 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define TSI721_IMD_CS 0x78000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define TSI721_IMD_HO 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __le32 bufptr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __le32 bufptr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 reserved[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } __aligned(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * Outbound Messaging Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct tsi721_omsg_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __le32 type_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define TSI721_OMD_DEVID 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define TSI721_OMD_CRF 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define TSI721_OMD_PRIO 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define TSI721_OMD_IOF 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define TSI721_OMD_DTYPE 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define TSI721_OMD_RSRVD 0x17f80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) __le32 msg_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define TSI721_OMD_BCOUNT 0x00000ff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define TSI721_OMD_SSIZE 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define TSI721_OMD_LETER 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define TSI721_OMD_XMBOX 0x003c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define TSI721_OMD_MBOX 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define TSI721_OMD_TT 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) __le32 bufptr_lo; /* if DTYPE == 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) __le32 next_lo; /* if DTYPE == 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __le32 bufptr_hi; /* if DTYPE == 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) __le32 next_hi; /* if DTYPE == 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct tsi721_dma_sts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) __le64 desc_sts[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) } __aligned(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct tsi721_desc_sts_fifo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) __le64 da64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __le32 lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) __le32 hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } da32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } stat[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) } __aligned(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Descriptor types for BDMA and Messaging blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) enum dma_dtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) DTYPE1 = 1, /* Data Transfer DMA Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) DTYPE2 = 2, /* Immediate Data Transfer DMA Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) DTYPE3 = 3, /* Block Pointer DMA Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) DTYPE4 = 4, /* Outbound Msg DMA Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) DTYPE6 = 6 /* Inbound Messaging Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) enum dma_rtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) NREAD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) LAST_NWRITE_R = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ALL_NWRITE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ALL_NWRITE_R = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MAINT_RD = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MAINT_WR = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * mport Driver Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define TSI721_DMA_CHNUM TSI721_DMA_MAXCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define TSI721_DMACH_MAINT 7 /* DMA channel for maint requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) enum tsi721_smsg_int_flag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SMSG_INT_NONE = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SMSG_INT_ECC_COR_CH = 0x000000ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SMSG_INT_ECC_NCOR_CH = 0x0000ff00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SMSG_INT_ECC_COR = 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) SMSG_INT_ECC_NCOR = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SMSG_INT_UNS_RSP = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) SMSG_INT_ALL = 0x0006ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #ifdef CONFIG_RAPIDIO_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define TSI721_BDMA_MAX_BCOUNT (TSI721_DMAD_BCOUNT1 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct tsi721_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct dma_async_tx_descriptor txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u16 destid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* low 64-bits of 66-bit RIO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u64 rio_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* upper 2-bits of 66-bit RIO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 rio_addr_u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) enum dma_rtype rtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct list_head desc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned int sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct tsi721_bdma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int bd_num; /* number of HW buffer descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) void *bd_base; /* start of DMA descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dma_addr_t bd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) void *sts_base; /* start of DMA BD status FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dma_addr_t sts_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int sts_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 sts_rdptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 wr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 wr_count_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct dma_chan dchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct tsi721_tx_desc *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct tsi721_tx_desc *active_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct list_head free_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct tsi721_bdma_maint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int ch_id; /* BDMA channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int bd_num; /* number of buffer descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) void *bd_base; /* start of DMA descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dma_addr_t bd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) void *sts_base; /* start of DMA BD status FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dma_addr_t sts_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int sts_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct tsi721_imsg_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* VA/PA of data buffers for incoming messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void *buf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dma_addr_t buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* VA/PA of circular free buffer list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) void *imfq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dma_addr_t imfq_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* VA/PA of Inbound message descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void *imd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dma_addr_t imd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Inbound Queue buffer pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) void *imq_base[TSI721_IMSGD_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u32 rx_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) void *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u32 fq_wrptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u32 desc_rdptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct tsi721_omsg_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* VA/PA of OB Msg descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) void *omd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dma_addr_t omd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* VA/PA of OB Msg data buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) void *omq_base[TSI721_OMSGD_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dma_addr_t omq_phys[TSI721_OMSGD_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* VA/PA of OB Msg descriptor status FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) void *sts_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dma_addr_t sts_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 sts_size; /* # of allocated status entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 sts_rdptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 tx_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) void *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 wr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) enum tsi721_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) TSI721_USING_MSI = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) TSI721_USING_MSIX = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) TSI721_IMSGID_SET = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * MSI-X Table Entries (0 ... 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define TSI721_MSIX_DMACH_DONE(x) (0 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define TSI721_MSIX_DMACH_INT(x) (8 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define TSI721_MSIX_BDMA_INT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define TSI721_MSIX_OMSG_DONE(x) (17 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define TSI721_MSIX_OMSG_INT(x) (25 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define TSI721_MSIX_IMSG_DQ_RCV(x) (33 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define TSI721_MSIX_IMSG_INT(x) (41 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define TSI721_MSIX_MSG_INT 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define TSI721_MSIX_SR2PC_IDBQ_RCV(x) (50 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define TSI721_MSIX_SR2PC_CH_INT(x) (58 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define TSI721_MSIX_SR2PC_INT 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define TSI721_MSIX_PC2SR_INT 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define TSI721_MSIX_SRIO_MAC_INT 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define TSI721_MSIX_I2C_INT 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* MSI-X vector and init table entry indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) enum tsi721_msix_vect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TSI721_VECT_IDB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) TSI721_VECT_PWRX, /* PW_RX is part of SRIO MAC Interrupt reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TSI721_VECT_OMB0_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) TSI721_VECT_OMB1_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) TSI721_VECT_OMB2_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) TSI721_VECT_OMB3_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) TSI721_VECT_OMB0_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) TSI721_VECT_OMB1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) TSI721_VECT_OMB2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) TSI721_VECT_OMB3_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TSI721_VECT_IMB0_RCV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) TSI721_VECT_IMB1_RCV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) TSI721_VECT_IMB2_RCV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) TSI721_VECT_IMB3_RCV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TSI721_VECT_IMB0_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) TSI721_VECT_IMB1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) TSI721_VECT_IMB2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) TSI721_VECT_IMB3_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #ifdef CONFIG_RAPIDIO_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) TSI721_VECT_DMA0_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) TSI721_VECT_DMA1_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) TSI721_VECT_DMA2_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) TSI721_VECT_DMA3_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) TSI721_VECT_DMA4_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) TSI721_VECT_DMA5_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) TSI721_VECT_DMA6_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) TSI721_VECT_DMA7_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) TSI721_VECT_DMA0_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) TSI721_VECT_DMA1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) TSI721_VECT_DMA2_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) TSI721_VECT_DMA3_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) TSI721_VECT_DMA4_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) TSI721_VECT_DMA5_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) TSI721_VECT_DMA6_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) TSI721_VECT_DMA7_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) TSI721_VECT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define IRQ_DEVICE_NAME_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct msix_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u16 vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) char irq_name[IRQ_DEVICE_NAME_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #endif /* CONFIG_PCI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct tsi721_ib_win_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dma_addr_t lstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct tsi721_ib_win {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u64 rstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dma_addr_t lstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) bool xlat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct list_head mappings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct tsi721_obw_bar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u64 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u64 free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct tsi721_ob_win {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u64 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u16 destid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u64 rstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct tsi721_obw_bar *pbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct tsi721_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct rio_mport mport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct msix_irq msix[TSI721_VECT_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Doorbells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) void __iomem *odb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) void *idb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dma_addr_t idb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct work_struct idb_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 db_discard_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Inbound Port-Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct work_struct pw_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct kfifo pw_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) spinlock_t pw_fifo_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 pw_discard_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* BDMA Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #ifdef CONFIG_RAPIDIO_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Inbound Messaging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int imsg_init[TSI721_IMSG_CHNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct tsi721_imsg_ring imsg_ring[TSI721_IMSG_CHNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Outbound Messaging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int omsg_init[TSI721_OMSG_CHNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* Inbound Mapping Windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct tsi721_ib_win ib_win[TSI721_IBWIN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int ibwin_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Outbound Mapping Windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct tsi721_obw_bar p2r_bar[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct tsi721_ob_win ob_win[TSI721_OBWIN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int obwin_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #ifdef CONFIG_RAPIDIO_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) extern int tsi721_register_dma(struct tsi721_device *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) extern void tsi721_unregister_dma(struct tsi721_device *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) extern void tsi721_dma_stop_all(struct tsi721_device *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define tsi721_dma_stop_all(priv) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define tsi721_unregister_dma(priv) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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