Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Sanechips Technology Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ZX_PWM_MODE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define ZX_PWM_CLKDIV_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ZX_PWM_CLKDIV_MASK	GENMASK(11, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define ZX_PWM_CLKDIV(x)	(((x) << ZX_PWM_CLKDIV_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 					 ZX_PWM_CLKDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ZX_PWM_POLAR		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ZX_PWM_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ZX_PWM_PERIOD		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ZX_PWM_DUTY		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ZX_PWM_CLKDIV_MAX	1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ZX_PWM_PERIOD_MAX	65535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct zx_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct clk *wclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static inline struct zx_pwm_chip *to_zx_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	return container_of(chip, struct zx_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			       unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	return readl(zpc->base + (hwpwm + 1) * 0x10 + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 				 unsigned int offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			    unsigned int offset, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	data = zx_pwm_readl(zpc, hwpwm, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	data |= value & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	zx_pwm_writel(zpc, hwpwm, offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void zx_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			     struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (value & ZX_PWM_POLAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		state->polarity = PWM_POLARITY_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (value & ZX_PWM_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	div = (value & ZX_PWM_CLKDIV_MASK) >> ZX_PWM_CLKDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	rate = clk_get_rate(zpc->wclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	tmp *= div * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	tmp *= div * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			 unsigned int duty_ns, unsigned int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned int period_cycles, duty_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* Find out the best divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	rate = clk_get_rate(zpc->wclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		c = rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		c = c * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		do_div(c, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		if (c < ZX_PWM_PERIOD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		if (div > ZX_PWM_CLKDIV_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* Calculate duty cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	period_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	c *= duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	do_div(c, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	duty_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * If the PWM is being enabled, we have to temporarily disable it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * before configuring the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* Set up registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_CLKDIV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			ZX_PWM_CLKDIV(div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* Re-enable the PWM if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				ZX_PWM_EN, ZX_PWM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int zx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct zx_pwm_chip *zpc = to_zx_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct pwm_state cstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	pwm_get_state(pwm, &cstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (state->polarity != cstate.polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_POLAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				(state->polarity == PWM_POLARITY_INVERSED) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				 0 : ZX_PWM_POLAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (state->period != cstate.period ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	    state->duty_cycle != cstate.duty_cycle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		ret = zx_pwm_config(chip, pwm, state->duty_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				    state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (state->enabled != cstate.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		if (state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			ret = clk_prepare_enable(zpc->wclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					ZX_PWM_EN, ZX_PWM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 					ZX_PWM_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			clk_disable_unprepare(zpc->wclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct pwm_ops zx_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.apply = zx_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.get_state = zx_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int zx_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct zx_pwm_chip *zpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (!zpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	zpc->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (IS_ERR(zpc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		return PTR_ERR(zpc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	zpc->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (IS_ERR(zpc->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return PTR_ERR(zpc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	zpc->wclk = devm_clk_get(&pdev->dev, "wclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (IS_ERR(zpc->wclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return PTR_ERR(zpc->wclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ret = clk_prepare_enable(zpc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	zpc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	zpc->chip.ops = &zx_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	zpc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	zpc->chip.npwm = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	zpc->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	zpc->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 * PWM devices may be enabled by firmware, and let's disable all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * them initially to save power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	for (i = 0; i < zpc->chip.npwm; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		zx_pwm_set_mask(zpc, i, ZX_PWM_MODE, ZX_PWM_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = pwmchip_add(&zpc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		clk_disable_unprepare(zpc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	platform_set_drvdata(pdev, zpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int zx_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct zx_pwm_chip *zpc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ret = pwmchip_remove(&zpc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	clk_disable_unprepare(zpc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct of_device_id zx_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{ .compatible = "zte,zx296718-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_DEVICE_TABLE(of, zx_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct platform_driver zx_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.name = "zx-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.of_match_table = zx_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.probe = zx_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.remove = zx_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) module_platform_driver(zx_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_ALIAS("platform:zx-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_DESCRIPTION("ZTE ZX PWM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_LICENSE("GPL v2");