^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/pwm/pwm-vt8500.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * SoC architecture allocates register space for 4 PWMs but only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 2 are currently implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VT8500_NR_PWMS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_CTRL(pwm) (((pwm) << 4) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_STATUS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CTRL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CTRL_INVERT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CTRL_AUTOLOAD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CTRL_STOP_IMM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CTRL_LOAD_PRESCALE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CTRL_LOAD_PERIOD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STATUS_CTRL_UPDATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STATUS_SCALAR_UPDATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STATUS_PERIOD_UPDATE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STATUS_DUTY_UPDATE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STATUS_ALL_UPDATE 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct vt8500_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int loops = msecs_to_loops(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 mask = bitmask << (nr << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (unlikely(!loops))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long period_cycles, prescale, pv, dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) err = clk_enable(vt8500->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(chip->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) c = clk_get_rate(vt8500->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) c = c * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) do_div(c, 1000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) period_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (period_cycles < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) period_cycles = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) prescale = (period_cycles - 1) / 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pv = period_cycles / (prescale + 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (pv > 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pv = 4095;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (prescale > 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clk_disable(vt8500->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) c = (unsigned long long)pv * duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) do_div(c, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dc = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val |= CTRL_AUTOLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk_disable(vt8500->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) err = clk_enable(vt8500->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_err(chip->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val |= CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val &= ~CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clk_disable(vt8500->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) val |= CTRL_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val &= ~CTRL_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct pwm_ops vt8500_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .enable = vt8500_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .disable = vt8500_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .config = vt8500_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .set_polarity = vt8500_pwm_set_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct of_device_id vt8500_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .compatible = "via,vt8500-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int vt8500_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct vt8500_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(&pdev->dev, "invalid devicetree node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) chip->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) chip->chip.ops = &vt8500_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) chip->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) chip->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) chip->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) chip->chip.npwm = VT8500_NR_PWMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) chip->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (IS_ERR(chip->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(&pdev->dev, "clock source not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return PTR_ERR(chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) chip->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (IS_ERR(chip->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return PTR_ERR(chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = clk_prepare(chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(&pdev->dev, "failed to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = pwmchip_add(&chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(&pdev->dev, "failed to add PWM chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_unprepare(chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int vt8500_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct vt8500_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_unprepare(chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return pwmchip_remove(&chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct platform_driver vt8500_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .probe = vt8500_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .remove = vt8500_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "vt8500-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .of_match_table = vt8500_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) module_platform_driver(vt8500_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_DESCRIPTION("VT8500 PWM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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