^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for TWL4030/6030 Generic Pulse Width Modulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * This driver handles the PWMs of TWL4030 and TWL6030.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * The TRM names for the PWMs on TWL4030 are: PWM0, PWM1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * TWL6030 also have two PWMs named in the TRM as PWM1, PWM2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TWL_PWM_MAX 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Registers, bits and macro for TWL4030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TWL4030_GPBR1_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TWL4030_PMBR1_REG 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* GPBR1 register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TWL4030_PWMXCLK_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TWL4030_PWMX_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TWL4030_PWMX_BITS (TWL4030_PWMX_ENABLE | TWL4030_PWMXCLK_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TWL4030_PWM_TOGGLE(pwm, x) ((x) << (pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* PMBR1 register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TWL4030_GPIO6_PWM0_MUTE_MASK (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TWL4030_GPIO6_PWM0_MUTE_PWM0 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TWL4030_GPIO7_VIBRASYNC_PWM1_MASK (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TWL4030_GPIO7_VIBRASYNC_PWM1_PWM1 (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Register, bits and macro for TWL6030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TWL6030_TOGGLE3_REG 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TWL6030_PWMXR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TWL6030_PWMXS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TWL6030_PWMXEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TWL6030_PWM_TOGGLE(pwm, x) ((x) << (pwm * 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct twl_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 twl6030_toggle3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 twl4030_pwm_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline struct twl_pwm_chip *to_twl(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return container_of(chip, struct twl_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int twl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int duty_cycle = DIV_ROUND_UP(duty_ns * TWL_PWM_MAX, period_ns) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 pwm_config[2] = { 1, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int base, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * To configure the duty period:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * On-cycle is set to 1 (the minimum allowed value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * The off time of 0 is not configurable, so the mapping is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 0 -> off cycle = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 1 -> off cycle = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 2 -> off cycle = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 126 - > off cycle 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 127 - > off cycle 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * When on cycle == off cycle the PWM will be always on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (duty_cycle == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) duty_cycle = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else if (duty_cycle > TWL_PWM_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) duty_cycle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) base = pwm->hwpwm * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pwm_config[1] = duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = twl_i2c_write(TWL_MODULE_PWM, pwm_config, base, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(chip->dev, "%s: Failed to configure PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int twl4030_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct twl_pwm_chip *twl = to_twl(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mutex_lock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_GPBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(chip->dev, "%s: Failed to read GPBR1\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_err(chip->dev, "%s: Failed to enable PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(chip->dev, "%s: Failed to enable PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mutex_unlock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void twl4030_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct twl_pwm_chip *twl = to_twl(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mutex_lock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_GPBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(chip->dev, "%s: Failed to read GPBR1\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_GPBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mutex_unlock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int twl4030_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct twl_pwm_chip *twl = to_twl(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 val, mask, bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (pwm->hwpwm == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mask = TWL4030_GPIO7_VIBRASYNC_PWM1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bits = TWL4030_GPIO7_VIBRASYNC_PWM1_PWM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mask = TWL4030_GPIO6_PWM0_MUTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bits = TWL4030_GPIO6_PWM0_MUTE_PWM0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mutex_lock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_PMBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(chip->dev, "%s: Failed to read PMBR1\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Save the current MUX configuration for the PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) twl->twl4030_pwm_mux &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) twl->twl4030_pwm_mux |= (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Select PWM functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_PMBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(chip->dev, "%s: Failed to request PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mutex_unlock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void twl4030_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct twl_pwm_chip *twl = to_twl(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (pwm->hwpwm == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mask = TWL4030_GPIO7_VIBRASYNC_PWM1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mask = TWL4030_GPIO6_PWM0_MUTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mutex_lock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, &val, TWL4030_PMBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(chip->dev, "%s: Failed to read PMBR1\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Restore the MUX configuration for the PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val |= (twl->twl4030_pwm_mux & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, val, TWL4030_PMBR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(chip->dev, "%s: Failed to free PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mutex_unlock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int twl6030_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct twl_pwm_chip *twl = to_twl(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mutex_lock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = twl->twl6030_toggle3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_err(chip->dev, "%s: Failed to enable PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) twl->twl6030_toggle3 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mutex_unlock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void twl6030_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct twl_pwm_chip *twl = to_twl(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mutex_lock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val = twl->twl6030_toggle3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, TWL6030_TOGGLE3_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(chip->dev, "%s: Failed to disable PWM\n", pwm->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) twl->twl6030_toggle3 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mutex_unlock(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct pwm_ops twl4030_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .config = twl_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .enable = twl4030_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .disable = twl4030_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .request = twl4030_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .free = twl4030_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct pwm_ops twl6030_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .config = twl_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .enable = twl6030_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .disable = twl6030_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int twl_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct twl_pwm_chip *twl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!twl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (twl_class_is_4030())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) twl->chip.ops = &twl4030_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) twl->chip.ops = &twl6030_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) twl->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) twl->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) twl->chip.npwm = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mutex_init(&twl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = pwmchip_add(&twl->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) platform_set_drvdata(pdev, twl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int twl_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct twl_pwm_chip *twl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return pwmchip_remove(&twl->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct of_device_id twl_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { .compatible = "ti,twl4030-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { .compatible = "ti,twl6030-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_DEVICE_TABLE(of, twl_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static struct platform_driver twl_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .name = "twl-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .of_match_table = of_match_ptr(twl_pwm_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .probe = twl_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .remove = twl_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) module_platform_driver(twl_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_DESCRIPTION("PWM driver for TWL4030 and TWL6030");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_ALIAS("platform:twl-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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