^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * EHRPWM PWM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* EHRPWM registers and bits definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Time base module registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TBCTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TBPRD 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TBCTL_PRDLD_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TBCTL_PRDLD_SHDW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TBCTL_PRDLD_IMDT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) BIT(8) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TBCTL_CTRMODE_UP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TBCTL_CTRMODE_DOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TBCTL_CTRMODE_UPDOWN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TBCTL_HSPCLKDIV_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TBCTL_CLKDIV_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLKDIV_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HSPCLKDIV_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PERIOD_MAX 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* compare module registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMPA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CMPB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Action qualifier module registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AQCTLA 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AQCTLB 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AQSFRC 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AQCSFRC 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AQCTL_CBU_MASK (BIT(9) | BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AQCTL_CBU_FRCLOW BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AQCTL_CBU_FRCHIGH BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AQCTL_CAU_MASK (BIT(5) | BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AQCTL_CAU_FRCLOW BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AQCTL_CAU_FRCHIGH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AQCTL_PRD_MASK (BIT(3) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AQCTL_PRD_FRCLOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AQCTL_PRD_FRCHIGH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AQCTL_ZRO_MASK (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AQCTL_ZRO_FRCLOW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AQCTL_ZRO_FRCHIGH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) AQCTL_ZRO_FRCHIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) AQCTL_ZRO_FRCLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) AQCTL_ZRO_FRCHIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) AQCTL_ZRO_FRCLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AQSFRC_RLDCSF_ZRO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AQSFRC_RLDCSF_PRD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AQSFRC_RLDCSF_ZROPRD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AQCSFRC_CSFB_FRCDIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AQCSFRC_CSFB_FRCLOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AQCSFRC_CSFB_FRCHIGH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AQCSFRC_CSFA_FRCDIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AQCSFRC_CSFA_FRCLOW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AQCSFRC_CSFA_FRCHIGH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ehrpwm_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 tbctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 tbprd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 cmpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 cmpb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 aqctla;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 aqctlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 aqsfrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 aqcsfrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct ehrpwm_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long period_cycles[NUM_PWM_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum pwm_polarity polarity[NUM_PWM_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk *tbclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ehrpwm_context ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return container_of(chip, struct ehrpwm_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return readw(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline void ehrpwm_write(void __iomem *base, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writew(value, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val = readw(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) val |= value & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writew(val, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * set_prescale_div - Set up the prescaler divider function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @rqst_prescaler: prescaler value min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @prescale_div: prescaler value set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @tb_clk_div: Time Base Control prescaler bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 *tb_clk_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int clkdiv, hspclkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * calculations for prescaler value :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * HSPCLKDIVIDER = 2 ** hspclkdiv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * CLKDIVIDER = (1), if clkdiv == 0 *OR*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * (2 * clkdiv), if clkdiv != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Configure prescale_div value such that period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * register value is less than 65535.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *prescale_div = (1 << clkdiv) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (hspclkdiv ? (hspclkdiv * 2) : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (*prescale_div > rqst_prescaler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u16 aqctl_val, aqctl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int aqctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Configure PWM output to HIGH/LOW level on counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * reaches compare register value and LOW/HIGH level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * on counter value reaches period register value and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * zero value on counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (chan == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) aqctl_reg = AQCTLB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) aqctl_mask = AQCTL_CBU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) aqctl_val = AQCTL_CHANB_POLINVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) aqctl_val = AQCTL_CHANB_POLNORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) aqctl_reg = AQCTLA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) aqctl_mask = AQCTL_CAU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) aqctl_val = AQCTL_CHANA_POLINVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) aqctl_val = AQCTL_CHANA_POLNORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 period_cycles, duty_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 ps_divval, tb_divval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int i, cmp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (period_ns > NSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) c = pc->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) c = c * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) do_div(c, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) period_cycles = (unsigned long)c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (period_cycles < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) period_cycles = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) duty_cycles = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) c = pc->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) c = c * duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) do_div(c, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) duty_cycles = (unsigned long)c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Period values should be same for multiple PWM channels as IP uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * same period register for multiple channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < NUM_PWM_CHANNEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (pc->period_cycles[i] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (pc->period_cycles[i] != period_cycles)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Allow channel to reconfigure period if no other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * channels being configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (i == pwm->hwpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "period value conflicts with channel %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pc->period_cycles[pwm->hwpwm] = period_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Configure clock prescaler to support Low frequency PWM wave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) &tb_divval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(chip->dev, "Unsupported values\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pm_runtime_get_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Update clock prescaler values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Update period & duty cycle with presacler division */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) period_cycles = period_cycles / ps_divval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) duty_cycles = duty_cycles / ps_divval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Configure shadow loading on Period register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Configure ehrpwm counter for up-count mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) TBCTL_CTRMODE_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (pwm->hwpwm == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Channel 1 configured with compare B register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cmp_reg = CMPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Channel 0 configured with compare A register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cmp_reg = CMPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pm_runtime_put_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Configuration of polarity in hardware delayed, do at enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pc->polarity[pwm->hwpwm] = polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u16 aqcsfrc_val, aqcsfrc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Leave clock enabled on enabling PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pm_runtime_get_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Disabling Action Qualifier on PWM output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (pwm->hwpwm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) aqcsfrc_val = AQCSFRC_CSFB_FRCDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) aqcsfrc_mask = AQCSFRC_CSFB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) aqcsfrc_val = AQCSFRC_CSFA_FRCDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) aqcsfrc_mask = AQCSFRC_CSFA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Changes to shadow mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) AQSFRC_RLDCSF_ZRO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Channels polarity can be configured from action qualifier module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) configure_polarity(pc, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Enable TBCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = clk_enable(pc->tbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_name(pc->chip.dev), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u16 aqcsfrc_val, aqcsfrc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Action Qualifier puts PWM output low forcefully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (pwm->hwpwm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) aqcsfrc_val = AQCSFRC_CSFB_FRCLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) aqcsfrc_mask = AQCSFRC_CSFB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) aqcsfrc_val = AQCSFRC_CSFA_FRCLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) aqcsfrc_mask = AQCSFRC_CSFA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Update shadow register first before modifying active register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) AQSFRC_RLDCSF_ZRO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Changes to immediate action on Action Qualifier. This puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Action Qualifier control on PWM output from next TBCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) AQSFRC_RLDCSF_IMDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Disabling TBCLK on PWM disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) clk_disable(pc->tbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Disable clock on PWM disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pm_runtime_put_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_warn(chip->dev, "Removing PWM device without disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pm_runtime_put_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* set period value to zero on free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pc->period_cycles[pwm->hwpwm] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct pwm_ops ehrpwm_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .free = ehrpwm_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .config = ehrpwm_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .set_polarity = ehrpwm_pwm_set_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .enable = ehrpwm_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .disable = ehrpwm_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct of_device_id ehrpwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { .compatible = "ti,am3352-ehrpwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { .compatible = "ti,am33xx-ehrpwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_DEVICE_TABLE(of, ehrpwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int ehrpwm_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct ehrpwm_pwm_chip *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) clk = devm_clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_warn(&pdev->dev, "Binding is obsolete.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clk = devm_clk_get(pdev->dev.parent, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pc->clk_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!pc->clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_err(&pdev->dev, "failed to get clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pc->chip.ops = &ehrpwm_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pc->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pc->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pc->chip.npwm = NUM_PWM_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (IS_ERR(pc->mmio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return PTR_ERR(pc->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Acquire tbclk for Time Base EHRPWM submodule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (IS_ERR(pc->tbclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(&pdev->dev, "Failed to get tbclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return PTR_ERR(pc->tbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = clk_prepare(pc->tbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = pwmchip_add(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto err_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) err_clk_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk_unprepare(pc->tbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int ehrpwm_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clk_unprepare(pc->tbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pm_runtime_get_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pm_runtime_put_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int ehrpwm_pwm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ehrpwm_pwm_save_context(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (i = 0; i < pc->chip.npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct pwm_device *pwm = &pc->chip.pwms[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Disable explicitly if PWM is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int ehrpwm_pwm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) for (i = 0; i < pc->chip.npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct pwm_device *pwm = &pc->chip.pwms[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Enable explicitly if PWM was running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ehrpwm_pwm_restore_context(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ehrpwm_pwm_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static struct platform_driver ehrpwm_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .name = "ehrpwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .of_match_table = ehrpwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .pm = &ehrpwm_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .probe = ehrpwm_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .remove = ehrpwm_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) module_platform_driver(ehrpwm_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MODULE_DESCRIPTION("EHRPWM PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MODULE_AUTHOR("Texas Instruments");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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