^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ECAP PWM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* ECAP registers and bits definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CAP1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CAP2 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CAP3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CAP4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ECCTL2 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ECCTL2_APWM_POL_LOW BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ECCTL2_APWM_MODE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ECCTL2_TSCTR_FREERUN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct ecap_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 cap3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 cap4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u16 ecctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct ecap_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ecap_context ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return container_of(chip, struct ecap_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 period_cycles, duty_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (period_ns > NSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) c = pc->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) c = c * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) do_div(c, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) period_cycles = (u32)c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (period_cycles < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) period_cycles = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) duty_cycles = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) c = pc->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) c = c * duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) do_div(c, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) duty_cycles = (u32)c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pm_runtime_get_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) value = readw(pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Configure APWM mode & disable sync option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writew(value, pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Update active registers if not running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel(duty_cycles, pc->mmio_base + CAP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel(period_cycles, pc->mmio_base + CAP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Update shadow registers to configure period and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * compare values. This helps current PWM period to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * complete on reconfiguring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel(duty_cycles, pc->mmio_base + CAP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(period_cycles, pc->mmio_base + CAP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) value = readw(pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Disable APWM mode to put APWM output Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) value &= ~ECCTL2_APWM_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writew(value, pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pm_runtime_put_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pm_runtime_get_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) value = readw(pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Duty cycle defines LOW period of PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) value |= ECCTL2_APWM_POL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Duty cycle defines HIGH period of PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) value &= ~ECCTL2_APWM_POL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writew(value, pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pm_runtime_put_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Leave clock enabled on enabling PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pm_runtime_get_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Enable 'Free run Time stamp counter mode' to start counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * and 'APWM mode' to enable APWM output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) value = readw(pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writew(value, pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Disable 'Free run Time stamp counter mode' to stop counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * and 'APWM mode' to put APWM output to low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) value = readw(pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writew(value, pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Disable clock on PWM disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pm_runtime_put_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_warn(chip->dev, "Removing PWM device without disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pm_runtime_put_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct pwm_ops ecap_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .free = ecap_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .config = ecap_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .set_polarity = ecap_pwm_set_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .enable = ecap_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .disable = ecap_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct of_device_id ecap_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .compatible = "ti,am3352-ecap" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .compatible = "ti,am33xx-ecap" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MODULE_DEVICE_TABLE(of, ecap_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int ecap_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct ecap_pwm_chip *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk = devm_clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_warn(&pdev->dev, "Binding is obsolete.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clk = devm_clk_get(pdev->dev.parent, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pc->clk_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!pc->clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_err(&pdev->dev, "failed to get clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pc->chip.ops = &ecap_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pc->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pc->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pc->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (IS_ERR(pc->mmio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return PTR_ERR(pc->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = pwmchip_add(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int ecap_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pm_runtime_get_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pm_runtime_put_sync(pc->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel(pc->ctx.cap3, pc->mmio_base + CAP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) writel(pc->ctx.cap4, pc->mmio_base + CAP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int ecap_pwm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pwm_device *pwm = pc->chip.pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ecap_pwm_save_context(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Disable explicitly if PWM is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int ecap_pwm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct pwm_device *pwm = pc->chip.pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Enable explicitly if PWM was running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ecap_pwm_restore_context(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct platform_driver ecap_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "ecap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .of_match_table = ecap_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .pm = &ecap_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .probe = ecap_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .remove = ecap_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) module_platform_driver(ecap_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DESCRIPTION("ECAP PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_AUTHOR("Texas Instruments");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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