Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * drivers/pwm/pwm-tegra.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Tegra pulse-width-modulation controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2010-2020, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Overview of Tegra Pulse Width Modulator Register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * 1. 13-bit: Frequency division (SCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * 2. 8-bit : Pulse division (DUTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * 3. 1-bit : Enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * The PWM clock frequency is divided by 256 before subdividing it based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * on the programmable frequency division value to generate the required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * frequency for PWM output. The maximum output frequency that can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * achieved is (max rate of source clock) / 256.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * 408 MHz/256 = 1.6 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * To achieve 100% duty cycle, program Bit [24] of this register to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * 1’b1. In which case the other bits [23:16] are set to don't care.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * -	When PWM is disabled, the output is driven to inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * -	It does not allow the current PWM period to complete and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *	stops abruptly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * -	If the register is reconfigured while PWM is running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *	it does not complete the currently running period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * -	If the user input duty is beyond acceptible limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *	-EINVAL is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PWM_ENABLE	(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PWM_DUTY_WIDTH	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PWM_DUTY_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PWM_SCALE_WIDTH	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PWM_SCALE_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct tegra_pwm_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/* Maximum IP frequency for given SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned long max_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct tegra_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct reset_control*rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned long min_period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	const struct tegra_pwm_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return container_of(chip, struct tegra_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return readl(chip->regs + (num << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			     unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	writel(val, chip->regs + (num << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			    int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned long long c = duty_ns, hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned long rate, required_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * nearest integer during division.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	c *= (1 << PWM_DUTY_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	val = (u32)c << PWM_DUTY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 *  min period = max clock limit >> PWM_DUTY_WIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (period_ns < pc->min_period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * cycles at the PWM clock rate will take period_ns nanoseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 * num_channels: If single instance of PWM controller has multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * channels (e.g. Tegra210 or older) then it is not possible to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * configure separate clock rates to each of the channels, in such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 * case the value stored during probe will be referred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * If every PWM controller instance has one channel respectively, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * nums_channels == 1 then only the clock rate can be modified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * dynamically (e.g. Tegra186 or Tegra194).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (pc->soc->num_channels == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		 * with the maximum possible rate that the controller can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		 * provide. Any further lower value can be derived by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		 * PFM bits[0:12].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		 * required_clk_rate is a reference rate for source clock and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * it is derived based on user requested period. By setting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * source clock rate as required_clk_rate, PWM controller will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 * be able to configure the requested period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		required_clk_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			(NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		err = clk_set_rate(pc->clk, required_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* Store the new rate for further references */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		pc->clk_rate = clk_get_rate(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	rate = pc->clk_rate >> PWM_DUTY_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * Since the actual PWM divider is the register's frequency divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * field plus 1, we need to decrement to get the correct value to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * write to the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (rate > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		rate--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * Make sure that the rate will fit in the register's frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * divider field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (rate >> PWM_SCALE_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	val |= rate << PWM_SCALE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * If the PWM channel is disabled, make sure to turn on the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * before writing the register. Otherwise, keep it enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (!pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		err = clk_prepare_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		val |= PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	pwm_writel(pc, pwm->hwpwm, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * If the PWM is not enabled, turn the clock off again to save power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		clk_disable_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	rc = clk_prepare_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	val = pwm_readl(pc, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	val |= PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	pwm_writel(pc, pwm->hwpwm, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	val = pwm_readl(pc, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	val &= ~PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	pwm_writel(pc, pwm->hwpwm, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	clk_disable_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct pwm_ops tegra_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.config = tegra_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.enable = tegra_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.disable = tegra_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int tegra_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct tegra_pwm_chip *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (!pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	pwm->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	pwm->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	pwm->regs = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (IS_ERR(pwm->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return PTR_ERR(pwm->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	platform_set_drvdata(pdev, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	pwm->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (IS_ERR(pwm->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return PTR_ERR(pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* Set maximum frequency of the IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 * The requested and configured frequency may differ due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 * clock register resolutions. Get the configured frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 * so that PWM period can be calculated more accurately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	pwm->clk_rate = clk_get_rate(pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Set minimum limit of PWM period for the IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	pwm->min_period_ns =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	    (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (IS_ERR(pwm->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		ret = PTR_ERR(pwm->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	reset_control_deassert(pwm->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	pwm->chip.ops = &tegra_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	pwm->chip.npwm = pwm->soc->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	ret = pwmchip_add(&pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		reset_control_assert(pwm->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int tegra_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (WARN_ON(!pc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	err = clk_prepare_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	reset_control_assert(pc->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	clk_disable_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int tegra_pwm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int tegra_pwm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct tegra_pwm_soc tegra20_pwm_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.num_channels = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.max_frequency = 48000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct tegra_pwm_soc tegra186_pwm_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.max_frequency = 102000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const struct tegra_pwm_soc tegra194_pwm_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.num_channels = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.max_frequency = 408000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct of_device_id tegra_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct dev_pm_ops tegra_pwm_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct platform_driver tegra_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.name = "tegra-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.of_match_table = tegra_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.pm = &tegra_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.probe = tegra_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.remove = tegra_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) module_platform_driver(tegra_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MODULE_DESCRIPTION("Tegra PWM controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MODULE_ALIAS("platform:tegra-pwm");