^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Allwinner sun4i Pulse Width Modulation Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - When outputing the source clock directly, the PWM logic will be bypassed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and the currently running period is not guaranteed to be completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PWM_CTRL_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PWM_CH_PRD_BASE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PWM_CH_PRD_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PWMCH_OFFSET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PWM_PRESCAL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PWM_PRESCAL_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PWM_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PWM_ACT_STATE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PWM_CLK_GATING BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PWM_MODE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PWM_PULSE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PWM_BYPASS BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWM_RDY_BASE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PWM_RDY_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PWM_PRD(prd) (((prd) - 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PWM_PRD_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PWM_DTY_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const u32 prescaler_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 24000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 36000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 72000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0, /* Actually 1 but tested separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct sun4i_pwm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bool has_prescaler_bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bool has_direct_mod_clk_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int npwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct sun4i_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) spinlock_t ctrl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const struct sun4i_pwm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long next_period[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return container_of(chip, struct sun4i_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return readl(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 val, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(val, chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void sun4i_pwm_get_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u64 clk_rate, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_rate = clk_get_rate(sun4i_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * PWM chapter in H6 manual has a diagram which explains that if bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * bit is set, no other setting has any meaning. Even more, experiment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * proved that also enable bit is ignored in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) sun4i_pwm->data->has_direct_mod_clk_output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sun4i_pwm->data->has_prescaler_bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) prescaler = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (prescaler == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) state->polarity = PWM_POLARITY_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct pwm_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 *dty, u32 *prd, unsigned int *prsclr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool *bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u64 clk_rate, div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int prescaler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clk_rate = clk_get_rate(sun4i_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) state->enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (state->period * clk_rate >= NSEC_PER_SEC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Skip calculation of other parameters if we bypass them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (*bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (sun4i_pwm->data->has_prescaler_bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* First, test without any prescaler when available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) prescaler = PWM_PRESCAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * When not using any prescaler, the clock period in nanoseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * is not an integer so round it half up instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * truncating to get less surprising values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) div = clk_rate * state->period + NSEC_PER_SEC / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) do_div(div, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (div - 1 > PWM_PRD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) prescaler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (prescaler == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Go up from the first divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int pval = prescaler_table[prescaler];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!pval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) div = clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) do_div(div, pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) div = div * state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) do_div(div, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (div - 1 <= PWM_PRD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (div - 1 > PWM_PRD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *prd = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) div *= state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) do_div(div, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *dty = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *prsclr = prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct pwm_state cstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 ctrl, duty = 0, period = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int delay_us, prescaler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pwm_get_state(pwm, &cstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!cstate.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = clk_prepare_enable(sun4i_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(chip->dev, "failed to enable PWM clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) &bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(chip->dev, "period exceeds the maximum value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!cstate.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk_disable_unprepare(sun4i_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) spin_lock(&sun4i_pwm->ctrl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (sun4i_pwm->data->has_direct_mod_clk_output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* We can skip other parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_unlock(&sun4i_pwm->ctrl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Prescaler changed, the clock has to be gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ctrl |= BIT_CH(prescaler, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) nsecs_to_jiffies(cstate.period + 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (state->polarity != PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spin_unlock(&sun4i_pwm->ctrl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* We need a full period to elapse before disabling the channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) now = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if ((delay_us / 500) > MAX_UDELAY_MS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) msleep(delay_us / 1000 + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_lock(&sun4i_pwm->ctrl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spin_unlock(&sun4i_pwm->ctrl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clk_disable_unprepare(sun4i_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct pwm_ops sun4i_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .apply = sun4i_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .get_state = sun4i_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .has_prescaler_bypass = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .npwm = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .has_prescaler_bypass = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .npwm = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .has_prescaler_bypass = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .npwm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .has_prescaler_bypass = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .has_direct_mod_clk_output = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .npwm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .has_prescaler_bypass = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .has_direct_mod_clk_output = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .npwm = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct of_device_id sun4i_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .compatible = "allwinner,sun4i-a10-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .data = &sun4i_pwm_dual_nobypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .compatible = "allwinner,sun5i-a10s-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .data = &sun4i_pwm_dual_bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .compatible = "allwinner,sun5i-a13-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .data = &sun4i_pwm_single_bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .compatible = "allwinner,sun7i-a20-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .data = &sun4i_pwm_dual_bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .compatible = "allwinner,sun8i-h3-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .data = &sun4i_pwm_single_bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .compatible = "allwinner,sun50i-a64-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .data = &sun50i_a64_pwm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .compatible = "allwinner,sun50i-h6-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .data = &sun50i_h6_pwm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int sun4i_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct sun4i_pwm_chip *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pwm->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!pwm->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pwm->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (IS_ERR(pwm->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return PTR_ERR(pwm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * All hardware variants need a source clock that is divided and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * then feeds the counter that defines the output wave form. In the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * device tree this clock is either unnamed or called "mod".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Some variants (e.g. H6) need another clock to access the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * hardware registers; this is called "bus".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * So we request "mod" first (and ignore the corner case that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * parent provides a "mod" clock while the right one would be the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * unnamed one of the PWM device) and if this is not found we fall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * back to the first clock of the PWM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (IS_ERR(pwm->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "get mod clock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!pwm->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pwm->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (IS_ERR(pwm->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) "get unnamed clock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (IS_ERR(pwm->bus_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return dev_err_probe(&pdev->dev, PTR_ERR(pwm->bus_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "get bus clock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (IS_ERR(pwm->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return dev_err_probe(&pdev->dev, PTR_ERR(pwm->rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "get reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Deassert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = reset_control_deassert(pwm->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ERR_PTR(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * We're keeping the bus clock on for the sake of simplicity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Actually it only needs to be on for hardware register accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = clk_prepare_enable(pwm->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ERR_PTR(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto err_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pwm->chip.ops = &sun4i_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pwm->chip.npwm = pwm->data->npwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pwm->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pwm->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) spin_lock_init(&pwm->ctrl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = pwmchip_add(&pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) goto err_pwm_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) platform_set_drvdata(pdev, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) err_pwm_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) clk_disable_unprepare(pwm->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) err_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) reset_control_assert(pwm->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int sun4i_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = pwmchip_remove(&pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clk_disable_unprepare(pwm->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reset_control_assert(pwm->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct platform_driver sun4i_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .name = "sun4i-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .of_match_table = sun4i_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .probe = sun4i_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .remove = sun4i_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) module_platform_driver(sun4i_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MODULE_ALIAS("platform:sun4i-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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