^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/stmpe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STMPE24XX_PWMCS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PWMCS_EN_PWM0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PWMCS_EN_PWM1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PWMCS_EN_PWM2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STMPE24XX_PWMIC0 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STMPE24XX_PWMIC1 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STMPE24XX_PWMIC2 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STMPE_PWM_24XX_PINBASE 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct stmpe_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct stmpe *stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 last_duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline struct stmpe_pwm *to_stmpe_pwm(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return container_of(chip, struct stmpe_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dev_err(chip->dev, "error reading PWM#%u control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) value = ret | BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_err(chip->dev, "error writing PWM#%u control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void stmpe_24xx_pwm_disable(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_err(chip->dev, "error reading PWM#%u control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) value = ret & ~BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev_err(chip->dev, "error writing PWM#%u control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* STMPE 24xx PWM instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SMAX 0x007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SMIN 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GTS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LOAD BIT(14) /* Only available on 2403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RAMPUP 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RAMPDOWN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PRESCALE_512 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STEPTIME_1 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BRANCH (BIT(15) | BIT(13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int stmpe_24xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int i, pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 program[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Make sure we are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) stmpe_24xx_pwm_disable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Connect the PWM to the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pin = pwm->hwpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* On STMPE2401 and 2403 pins 21,22,23 are used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (stmpe_pwm->stmpe->partnum == STMPE2401 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) stmpe_pwm->stmpe->partnum == STMPE2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pin += STMPE_PWM_24XX_PINBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = stmpe_set_altfunc(stmpe_pwm->stmpe, BIT(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) STMPE_BLOCK_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_err(chip->dev, "unable to connect PWM#%u to pin\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* STMPE24XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) switch (pwm->hwpwm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) offset = STMPE24XX_PWMIC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) offset = STMPE24XX_PWMIC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) offset = STMPE24XX_PWMIC2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Should not happen as npwm is 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_dbg(chip->dev, "PWM#%u: config duty %d ns, period %d ns\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pwm->hwpwm, duty_ns, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (duty_ns == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (stmpe_pwm->stmpe->partnum == STMPE2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) program[0] = SMAX; /* off all the time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (stmpe_pwm->stmpe->partnum == STMPE2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) program[0] = LOAD | 0xff; /* LOAD 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) stmpe_pwm->last_duty = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else if (duty_ns == period_ns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (stmpe_pwm->stmpe->partnum == STMPE2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) program[0] = SMIN; /* on all the time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (stmpe_pwm->stmpe->partnum == STMPE2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) program[0] = LOAD | 0x00; /* LOAD 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) stmpe_pwm->last_duty = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 value, last = stmpe_pwm->last_duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Counter goes from 0x00 to 0xff repeatedly at 32768 Hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * (means a period of 30517 ns) then this is compared to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * counter from the ramp, if this is >= PWM counter the output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * is high. With LOAD we can define how much of the cycle it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * is on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Prescale = 0 -> 2 kHz -> T = 1/f = 488281.25 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Scale to 0..0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) duty = duty_ns * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) duty = DIV_ROUND_CLOSEST(duty, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) value = duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (value == last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Run the old program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) stmpe_24xx_pwm_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else if (stmpe_pwm->stmpe->partnum == STMPE2403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* STMPE2403 can simply set the right PWM value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) program[0] = LOAD | value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) program[1] = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else if (stmpe_pwm->stmpe->partnum == STMPE2401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* STMPE2401 need a complex program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u16 incdec = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (last < value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Count up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) incdec = RAMPUP | (value - last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Count down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) incdec = RAMPDOWN | (last - value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Step to desired value, smoothly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) program[0] = PRESCALE_512 | STEPTIME_1 | incdec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Loop eternally to 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) program[1] = BRANCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_dbg(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "PWM#%u: value = %02x, last_duty = %02x, program=%04x,%04x,%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pwm->hwpwm, value, last, program[0], program[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) program[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) stmpe_pwm->last_duty = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * We can write programs of up to 64 16-bit words into this channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) for (i = 0; i < ARRAY_SIZE(program); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) value = (program[i] >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = stmpe_reg_write(stmpe_pwm->stmpe, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(chip->dev, "error writing register %02x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) value = program[i] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = stmpe_reg_write(stmpe_pwm->stmpe, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_err(chip->dev, "error writing register %02x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) offset, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* If we were enabled, re-enable this PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) stmpe_24xx_pwm_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Sleep for 200ms so we're sure it will take effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_dbg(chip->dev, "programmed PWM#%u, %u bytes\n", pwm->hwpwm, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct pwm_ops stmpe_24xx_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .config = stmpe_24xx_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .enable = stmpe_24xx_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .disable = stmpe_24xx_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int __init stmpe_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct stmpe_pwm *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pwm->stmpe = stmpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (stmpe->partnum == STMPE2401 || stmpe->partnum == STMPE2403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pwm->chip.ops = &stmpe_24xx_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pwm->chip.npwm = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (stmpe->partnum == STMPE1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(&pdev->dev, "STMPE1601 not yet supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(&pdev->dev, "Unknown STMPE PWM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = stmpe_enable(stmpe, STMPE_BLOCK_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = pwmchip_add(&pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) stmpe_disable(stmpe, STMPE_BLOCK_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) platform_set_drvdata(pdev, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct platform_driver stmpe_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .name = "stmpe-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) builtin_platform_driver_probe(stmpe_pwm_driver, stmpe_pwm_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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