^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Gerald Baeza <gerald.baeza@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Inspired by timer-stm32.c from Maxime Coquelin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * pwm-atmel.c from Bo Shen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/stm32-timers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CCMR_CHANNEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CCMR_CHANNEL_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX_BREAKINPUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct stm32_breakinput {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct stm32_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct mutex lock; /* protect pwm config/enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 max_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bool have_complementary_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int num_breakinputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return container_of(chip, struct stm32_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static u32 active_channels(struct stm32_pwm *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 ccer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) regmap_read(dev->regmap, TIM_CCER, &ccer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ccer & TIM_CCER_CCXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch (ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return regmap_write(dev->regmap, TIM_CCR1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return regmap_write(dev->regmap, TIM_CCR2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return regmap_write(dev->regmap, TIM_CCR3, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return regmap_write(dev->regmap, TIM_CCR4, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Capture using PWM input mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * ___ ___
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * TI[1, 2, 3 or 4]: ........._| |________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * ^0 ^1 ^2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * . . .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * . . XXXXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * . . XXXXX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * . XXXXX . |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * XXXXX . . |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * COUNTER: ______XXXXX . . . |_XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * start^ . . . ^stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * . . . .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * v v . v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * CCR1/CCR3: tx..........t0...........t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * CCR2/CCR4: tx..............t1.........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * DMA burst transfer: | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * v v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * DMA buffer: { t0, tx } { t2, t1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * DMA done: ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * DMA done, compute:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * - Period = t2 - t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * - Duty cycle = t1 - t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long tmo_ms, u32 *raw_prd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 *raw_dty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device *parent = priv->chip.dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum stm32_timers_dmas dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 ccen, ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Ensure registers have been updated, enable counter and capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * or { CCR3, CCR4 }, { CCR3, CCR4 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 2, tmo_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Period: t2 - t0 (take care of counter overflow) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (priv->capture[0] <= priv->capture[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *raw_prd = priv->capture[2] - priv->capture[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Duty cycle capture requires at least two capture units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (pwm->chip->npwm < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *raw_dty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) else if (priv->capture[0] <= priv->capture[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *raw_dty = priv->capture[3] - priv->capture[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (*raw_dty > *raw_prd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Race beetween PWM input and DMA: it may happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * falling edge triggers new capture on TI2/4 before DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * had a chance to read CCR2/4. It means capture[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * contains period + duty_cycle. So, subtract period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *raw_dty -= *raw_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct pwm_capture *result, unsigned long tmo_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long long prd, div, dty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int psc = 0, icpsc, scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 raw_prd = 0, raw_dty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (active_channels(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_err(priv->chip.dev, "failed to enable counter clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* prescaler: fit timeout window provided by upper layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) div = (unsigned long long)rate * (unsigned long long)tmo_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) do_div(div, MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) prd = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) psc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) div = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) do_div(div, psc + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) regmap_write(priv->regmap, TIM_PSC, psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) regmap_update_bits(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) TIM_CCER_CC2P : TIM_CCER_CC4P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Got a capture. Try to improve accuracy at high rates:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * - decrease counter clock prescaler, scale up to max rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * - use input prescaler, capture once every /2 /4 or /8 edges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (raw_prd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) scale = max_arr / min(max_arr, raw_prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) scale = priv->max_arr; /* bellow resolution, use max scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (psc && scale > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* 2nd measure with new scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) psc /= scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) regmap_write(priv->regmap, TIM_PSC, psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) &raw_dty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Compute intermediate period not to exceed timeout at low rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) do_div(prd, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* input prescaler: also keep arbitrary margin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!icpsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Last chance to improve period accuracy, using input prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) regmap_update_bits(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (raw_dty >= (raw_prd >> icpsc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * We may fall here using input prescaler, when input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * capture starts on high side (before falling edge).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Example with icpsc to capture on each 4 events:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * start 1st capture 2nd capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * v v v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * ___ _____ _____ _____ _____ ____
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * TI1..4 |__| |__| |__| |__| |__|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * v v . . . . . v v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * icpsc1/3: . 0 . 1 . 2 . 3 . 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * icpsc2/4: 0 1 2 3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * v v v v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * CCR1/3 ......t0..............................t2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * CCR2/4 ..t1..............................t1'...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * . . .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Capture0: .<----------------------------->.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Capture1: .<-------------------------->. .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * . . .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Period: .<------> . .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Low side: .<>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Result:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * - Period = Capture0 / icpsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * - Duty = Period - Low side = Period - (Capture0 - Capture1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_write(priv->regmap, TIM_CCER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regmap_write(priv->regmap, TIM_PSC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clk_dis:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned long long prd, div, dty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int prescaler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 ccmr, mask, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Period and prescaler values depends on clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) do_div(div, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) prd = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) while (div > priv->max_arr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) prescaler++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) div = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) do_div(div, prescaler + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) prd = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (prescaler > MAX_TIM_PSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * All channels share the same prescaler and counter so when two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * channels are active at the same time we can't change them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (active_channels(priv) & ~(1 << ch * 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 psc, arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) regmap_read(priv->regmap, TIM_PSC, &psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) regmap_read(priv->regmap, TIM_ARR, &arr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if ((psc != prescaler) || (arr != prd - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) regmap_write(priv->regmap, TIM_PSC, prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) regmap_write(priv->regmap, TIM_ARR, prd - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Calculate the duty cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dty = prd * duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) do_div(dty, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) write_ccrx(priv, ch, dty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Configure output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mask = CCMR_CHANNEL_MASK << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ch < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mask = TIM_CCER_CC1P << (ch * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (priv->have_complementary_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mask |= TIM_CCER_CC1NP << (ch * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) regmap_update_bits(priv->regmap, TIM_CCER, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) polarity == PWM_POLARITY_NORMAL ? 0 : mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Enable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mask = TIM_CCER_CC1E << (ch * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (priv->have_complementary_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mask |= TIM_CCER_CC1NE << (ch * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Make sure that registers are updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Enable controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Disable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mask = TIM_CCER_CC1E << (ch * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (priv->have_complementary_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mask |= TIM_CCER_CC1NE << (ch * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* When all channels are disabled, we can disable the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!active_channels(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) enabled = pwm->state.enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (enabled && !state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) stm32_pwm_disable(priv, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (state->polarity != pwm->state.polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = stm32_pwm_config(priv, pwm->hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) state->duty_cycle, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!enabled && state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = stm32_pwm_enable(priv, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* protect common prescaler for all active channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = stm32_pwm_apply(chip, pwm, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct pwm_ops stm32pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .apply = stm32_pwm_apply_locked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) const struct stm32_breakinput *bi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 bke = TIM_BDTR_BKE(bi->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 bkp = TIM_BDTR_BKP(bi->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 bkf = TIM_BDTR_BKF(bi->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 mask = bkf | bkp | bke;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 bdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (bi->level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bdtr |= bkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) regmap_read(priv->regmap, TIM_BDTR, &bdtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return (bdtr & bke) ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) for (i = 0; i < priv->num_breakinputs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int nb, ret, array_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) nb = of_property_count_elems_of_size(np, "st,breakinput",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sizeof(struct stm32_breakinput));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Because "st,breakinput" parameter is optional do not make probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * failed if it doesn't exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (nb <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (nb > MAX_BREAKINPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) priv->num_breakinputs = nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = of_property_read_u32_array(np, "st,breakinput",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) (u32 *)priv->breakinputs, array_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (i = 0; i < priv->num_breakinputs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (priv->breakinputs[i].index > 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) priv->breakinputs[i].level > 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) priv->breakinputs[i].filter > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return stm32_pwm_apply_breakinputs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 ccer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * If complementary bit doesn't exist writing 1 will have no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * effect so we can detect it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regmap_update_bits(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) regmap_read(priv->regmap, TIM_CCER, &ccer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) priv->have_complementary_output = (ccer != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 ccer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int npwm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * If channels enable bits don't exist writing 1 will have no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * effect so we can detect and count them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) regmap_update_bits(priv->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) regmap_read(priv->regmap, TIM_CCER, &ccer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ccer & TIM_CCER_CC1E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) npwm++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ccer & TIM_CCER_CC2E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) npwm++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ccer & TIM_CCER_CC3E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) npwm++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ccer & TIM_CCER_CC4E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) npwm++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return npwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int stm32_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct stm32_pwm *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) priv->regmap = ddata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) priv->clk = ddata->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) priv->max_arr = ddata->max_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) priv->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) priv->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!priv->regmap || !priv->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = stm32_pwm_probe_breakinputs(priv, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) stm32_pwm_detect_complementary(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) priv->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) priv->chip.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) priv->chip.ops = &stm32pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) priv->chip.npwm = stm32_pwm_detect_channels(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = pwmchip_add(&priv->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int stm32_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct stm32_pwm *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) for (i = 0; i < priv->chip.npwm; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pwm_disable(&priv->chip.pwms[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pwmchip_remove(&priv->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int __maybe_unused stm32_pwm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct stm32_pwm *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 ccer, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Look for active channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ccer = active_channels(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) for (i = 0; i < priv->chip.npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mask = TIM_CCER_CC1E << (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ccer & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(dev, "PWM %u still in use by consumer %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) i, priv->chip.pwms[i].label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int __maybe_unused stm32_pwm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct stm32_pwm *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* restore breakinput registers that may have been lost in low power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return stm32_pwm_apply_breakinputs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const struct of_device_id stm32_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { .compatible = "st,stm32-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { /* end node */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static struct platform_driver stm32_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .probe = stm32_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .remove = stm32_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "stm32-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .of_match_table = stm32_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .pm = &stm32_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) module_platform_driver(stm32_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) MODULE_ALIAS("platform:stm32-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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