^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * STM32 Low-Power Timer PWM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Gerald Baeza <gerald.baeza@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Inspired by Gerald Baeza's pwm-stm32 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/stm32-lptimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct stm32_pwm_lp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return container_of(chip, struct stm32_pwm_lp, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STM32_LPTIM_MAX_PRESCALER 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long long prd, div, dty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pwm_state cstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 val, mask, cfgr, presc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool reenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pwm_get_state(pwm, &cstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) reenable = !cstate.enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (cstate.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Disable LP timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* disable clock to PWM counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Calculate the period and prescaler value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) do_div(div, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (!div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Clock is too slow to achieve requested period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_dbg(priv->chip.dev, "Can't reach %llu ns\n", state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) prd = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) while (div > STM32_LPTIM_MAX_ARR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) presc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(priv->chip.dev, "max prescaler exceeded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) div = prd >> presc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) prd = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Calculate the duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dty = prd * state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) do_div(dty, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!cstate.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* enable clock to drive PWM counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val = FIELD_PREP(STM32_LPTIM_PRESC, presc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Must disable LP timer to modify CFGR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reenable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (reenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Must (re)enable LP timer to modify CMP & ARR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = regmap_write(priv->regmap, STM32_LPTIM_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) STM32_LPTIM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* ensure CMP & ARR registers are properly written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) (val & STM32_LPTIM_CMPOK_ARROK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 100, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(priv->chip.dev, "ARR/CMP registers write issue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) STM32_LPTIM_CMPOKCF_ARROKCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (reenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Start LP timer in continuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) STM32_LPTIM_CNTSTRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) STM32_LPTIM_CNTSTRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!cstate.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void stm32_pwm_lp_get_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 val, presc, prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Keep PWM counter clock refcount in sync with PWM initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) presc = FIELD_GET(STM32_LPTIM_PRESC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tmp = prd + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tmp = (tmp << presc) * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) regmap_read(priv->regmap, STM32_LPTIM_CMP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) tmp = prd - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tmp = (tmp << presc) * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct pwm_ops stm32_pwm_lp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .apply = stm32_pwm_lp_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .get_state = stm32_pwm_lp_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int stm32_pwm_lp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct stm32_pwm_lp *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->regmap = ddata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) priv->clk = ddata->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) priv->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) priv->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) priv->chip.ops = &stm32_pwm_lp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) priv->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) priv->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) priv->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = pwmchip_add(&priv->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int stm32_pwm_lp_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct stm32_pwm_lp *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return pwmchip_remove(&priv->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int __maybe_unused stm32_pwm_lp_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct stm32_pwm_lp *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct pwm_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pwm_get_state(&priv->chip.pwms[0], &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (state.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "The consumer didn't stop us (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) priv->chip.pwms[0].label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int __maybe_unused stm32_pwm_lp_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) stm32_pwm_lp_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct of_device_id stm32_pwm_lp_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .compatible = "st,stm32-pwm-lp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct platform_driver stm32_pwm_lp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .probe = stm32_pwm_lp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .remove = stm32_pwm_lp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .name = "stm32-pwm-lp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .of_match_table = of_match_ptr(stm32_pwm_lp_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .pm = &stm32_pwm_lp_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) module_platform_driver(stm32_pwm_lp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_ALIAS("platform:stm32-pwm-lp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_DESCRIPTION("STMicroelectronics STM32 PWM LP driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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