^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PWM device driver for ST SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Ajit Pal Singh <ajitpal.singh@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Lee Jones <lee.jones@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STI_PWM_CTRL 0x50 /* Control/Config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STI_INT_STA 0x58 /* Interrupt Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PWM_INT_ACK 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PWM_PRESCALE_LOW_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PWM_PRESCALE_HIGH_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PWM_CPT_EDGE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PWM_INT_ACK_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STI_MAX_CPT_DEVS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPT_DC_MAX 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Regfield IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Bits in PWM_CTRL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PWMCLK_PRESCALE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PWMCLK_PRESCALE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CPTCLK_PRESCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PWM_OUT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PWM_CPT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PWM_CPT_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PWM_CPT_INT_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Keep last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MAX_REGFIELDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Each capture input can be programmed to detect rising-edge, falling-edge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * either edge or neither egde.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum sti_cpt_edge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CPT_EDGE_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CPT_EDGE_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CPT_EDGE_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CPT_EDGE_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct sti_cpt_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 snapshot[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct sti_pwm_compat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const struct reg_field *reg_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int pwm_num_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int cpt_num_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int max_pwm_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int max_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct sti_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk *pwm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *cpt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct sti_pwm_compat_data *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct regmap_field *prescale_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regmap_field *prescale_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regmap_field *pwm_out_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct regmap_field *pwm_cpt_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct regmap_field *pwm_cpt_int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct regmap_field *pwm_cpt_int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct pwm_device *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long configured;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int en_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return container_of(chip, struct sti_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Calculate the prescaler value corresponding to the period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int *prescale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct sti_pwm_compat_data *cdata = pc->cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clk_rate = clk_get_rate(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_err(pc->dev, "failed to get clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) value = NSEC_PER_SEC / clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) value *= cdata->max_pwm_cnt + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (period % value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ps = period / value - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ps > cdata->max_prescale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *prescale = ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * only way to change the period (apart from changing the PWM input clock) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * to change the PWM clock prescaler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * period values are supported (for a particular clock rate). The requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * period will be applied only if it matches one of these 256 values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sti_pwm_compat_data *cdata = pc->cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int ncfg, value, prescale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct pwm_device *cur = pc->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device *dev = pc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool period_same = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ncfg = hweight_long(pc->configured);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ncfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) period_same = (period_ns == pwm_get_period(cur));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Allow configuration changes if one of the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * satisfy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * 1. No devices have been configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * 2. Only one device has been configured and the new request is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * the same device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * 3. Only one device has been configured and the new request is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * a new device and period of the new device is same as the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * configured period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * 4. More than one devices are configured and period of the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * requestis the same as the current period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!ncfg ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ((ncfg > 1) && period_same)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Enable clock before writing to PWM registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = clk_enable(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = clk_enable(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!period_same) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) value = prescale & PWM_PRESCALE_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = regmap_field_write(pc->prescale_low, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = regmap_field_write(pc->prescale_high, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * When PWMVal == 0, PWM pulse = 1 local clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * When PWMVal == max_pwm_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * PWM pulse = (max_pwm_count + 1) local cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * that is continuous pulse: signal never goes low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) value = cdata->max_pwm_cnt * duty_ns / period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = regmap_field_write(pc->pwm_cpt_int_en, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) set_bit(pwm->hwpwm, &pc->configured);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pc->cur = pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) prescale, period_ns, duty_ns, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clk_dis:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clk_disable(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk_disable(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct device *dev = pc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Since we have a common enable for all PWM devices, do not enable if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * already enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mutex_lock(&pc->sti_pwm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!pc->en_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = clk_enable(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = clk_enable(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = regmap_field_write(pc->pwm_out_en, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(dev, "failed to enable PWM device %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pwm->hwpwm, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pc->en_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mutex_unlock(&pc->sti_pwm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mutex_lock(&pc->sti_pwm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (--pc->en_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mutex_unlock(&pc->sti_pwm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) regmap_field_write(pc->pwm_out_en, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk_disable(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) clk_disable(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mutex_unlock(&pc->sti_pwm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clear_bit(pwm->hwpwm, &pc->configured);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct pwm_capture *result, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct sti_pwm_compat_data *cdata = pc->cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct sti_cpt_ddata *ddata = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct device *dev = pc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int effective_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned long long high, low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (pwm->hwpwm >= cdata->cpt_num_devs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(dev, "device %u is not valid\n", pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mutex_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ddata->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Prepare capture measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Enable capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = regmap_field_write(pc->pwm_cpt_en, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(dev, "failed to enable PWM capture %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pwm->hwpwm, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) msecs_to_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret == -ERESTARTSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) switch (ddata->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Getting here could mean:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * - input signal is constant of less than 1 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * - there is no input signal at all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * In such case the frequency is rounded down to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) result->period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) result->duty_cycle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* We have everying we need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) high = ddata->snapshot[1] - ddata->snapshot[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) low = ddata->snapshot[2] - ddata->snapshot[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) effective_ticks = clk_get_rate(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) result->period = (high + low) * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) result->period /= effective_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) result->duty_cycle = high * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) result->duty_cycle /= effective_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(dev, "internal error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Disable capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) regmap_field_write(pc->pwm_cpt_en, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mutex_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct pwm_ops sti_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .capture = sti_pwm_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .config = sti_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .enable = sti_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .disable = sti_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .free = sti_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static irqreturn_t sti_pwm_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct sti_pwm_chip *pc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct device *dev = pc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct sti_cpt_ddata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int devicenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int cpt_int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) while (cpt_int_stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) devicenum = ffs(cpt_int_stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ddata = pwm_get_chip_data(&pc->chip.pwms[devicenum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * Capture input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * _______ _______
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * __| |_________________| |________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * ^0 ^1 ^2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Capture start by the first available rising edge. When a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * capture event occurs, capture value (CPT_VALx) is stored,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * index incremented, capture edge changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * After the capture, if the index > 1, we have collected the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * necessary data so we signal the thread waiting for it and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * disable the capture by setting capture edge to none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) regmap_read(pc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PWM_CPT_VAL(devicenum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &ddata->snapshot[ddata->index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) switch (ddata->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) reg ^= PWM_CPT_EDGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ddata->index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) regmap_write(pc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PWM_CPT_EDGE(devicenum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) CPT_EDGE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) wake_up(&ddata->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(dev, "Internal error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cpt_int_stat &= ~BIT_MASK(devicenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Just ACK everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct device *dev = pc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) const struct reg_field *reg_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct sti_pwm_compat_data *cdata = pc->cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 num_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cdata->pwm_num_devs = num_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cdata->cpt_num_devs = num_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!cdata->pwm_num_devs && !cdata->cpt_num_devs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(dev, "No channels configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) reg_fields = cdata->reg_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reg_fields[PWMCLK_PRESCALE_LOW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (IS_ERR(pc->prescale_low))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return PTR_ERR(pc->prescale_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) reg_fields[PWMCLK_PRESCALE_HIGH]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (IS_ERR(pc->prescale_high))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return PTR_ERR(pc->prescale_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) reg_fields[PWM_OUT_EN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (IS_ERR(pc->pwm_out_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return PTR_ERR(pc->pwm_out_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) reg_fields[PWM_CPT_EN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (IS_ERR(pc->pwm_cpt_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return PTR_ERR(pc->pwm_cpt_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) reg_fields[PWM_CPT_INT_EN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (IS_ERR(pc->pwm_cpt_int_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return PTR_ERR(pc->pwm_cpt_int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reg_fields[PWM_CPT_INT_STAT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return PTR_ERR(pc->pwm_cpt_int_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct regmap_config sti_pwm_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int sti_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct sti_pwm_compat_data *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct sti_pwm_chip *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!cdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pc->mmio = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (IS_ERR(pc->mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return PTR_ERR(pc->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) &sti_pwm_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (IS_ERR(pc->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return PTR_ERR(pc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pdev->name, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(&pdev->dev, "Failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Setup PWM data with default values: some values could be replaced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * with specific ones provided from Device Tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) cdata->reg_fields = sti_pwm_regfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) cdata->max_prescale = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) cdata->max_pwm_cnt = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) cdata->pwm_num_devs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cdata->cpt_num_devs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pc->cdata = cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pc->en_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mutex_init(&pc->sti_pwm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = sti_pwm_probe_dt(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!cdata->pwm_num_devs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto skip_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (IS_ERR(pc->pwm_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_err(dev, "failed to get PWM clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return PTR_ERR(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = clk_prepare(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_err(dev, "failed to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) skip_pwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!cdata->cpt_num_devs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) goto skip_cpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (IS_ERR(pc->cpt_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_err(dev, "failed to get PWM capture clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return PTR_ERR(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = clk_prepare(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(dev, "failed to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) skip_cpt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pc->chip.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pc->chip.ops = &sti_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pc->chip.npwm = pc->cdata->pwm_num_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = pwmchip_add(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) clk_unprepare(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) clk_unprepare(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) for (i = 0; i < cdata->cpt_num_devs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct sti_cpt_ddata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) init_waitqueue_head(&ddata->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mutex_init(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pwm_set_chip_data(&pc->chip.pwms[i], ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int sti_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) for (i = 0; i < pc->cdata->pwm_num_devs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pwm_disable(&pc->chip.pwms[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) clk_unprepare(pc->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) clk_unprepare(pc->cpt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const struct of_device_id sti_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { .compatible = "st,sti-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static struct platform_driver sti_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .name = "sti-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .of_match_table = sti_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .probe = sti_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .remove = sti_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) module_platform_driver(sti_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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