^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SPRD_PWM_PRESCALE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SPRD_PWM_MOD 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPRD_PWM_DUTY 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPRD_PWM_ENABLE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPRD_PWM_MOD_MAX GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPRD_PWM_DUTY_MSK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRD_PWM_ENABLE_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_PWM_CHN_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPRD_PWM_REGS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_PWM_CHN_CLKS_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPRD_PWM_CHN_OUTPUT_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct sprd_pwm_chn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct sprd_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int num_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The list of clocks required by PWM channels, and each channel has 2 clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * enable clock and pwm clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char * const sprd_pwm_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "enable0", "pwm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "enable1", "pwm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "enable2", "pwm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "enable3", "pwm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return readl_relaxed(spc->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel_relaxed(val, spc->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct sprd_pwm_chip *spc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) container_of(chip, struct sprd_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 val, duty, prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * The clocks to PWM channel has to be enabled first before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * reading to the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(spc->dev, "failed to enable pwm%u clocks\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (val & SPRD_PWM_ENABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * The hardware provides a counter that is feed by the source clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * The period length is (PRESCALE + 1) * MOD counter steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Thus the period_ns and duty_ns calculation formula should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) prescale = val & SPRD_PWM_PRESCALE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) duty = val & SPRD_PWM_DUTY_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tmp = (prescale + 1) * NSEC_PER_SEC * duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Disable PWM clocks if the PWM channel is not in enable state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 prescale, duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * The hardware provides a counter that is feed by the source clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * The period length is (PRESCALE + 1) * MOD counter steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * The value for PRESCALE is selected such that the resulting period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * gets the maximal length not bigger than the requested one with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * given settings (MOD = SPRD_PWM_MOD_MAX and input clock).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tmp = (u64)chn->clk_rate * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) do_div(tmp, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (prescale > SPRD_PWM_PRESCALE_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) prescale = SPRD_PWM_PRESCALE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Note: Writing DUTY triggers the hardware to actually apply the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * values written to MOD and DUTY to the output, so must keep writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * DUTY last.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * The hardware can ensures that current running period is completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * before changing a new configuration to avoid mixed settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct sprd_pwm_chip *spc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) container_of(chip, struct sprd_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct pwm_state *cstate = &pwm->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!cstate->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * The clocks to PWM channel has to be enabled first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * before writing to the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) chn->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(spc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "failed to enable pwm%u clocks\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } else if (cstate->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Note: After setting SPRD_PWM_ENABLE to zero, the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * will not wait for current period to be completed, instead it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * will stop the PWM channel immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct pwm_ops sprd_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .apply = sprd_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .get_state = sprd_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct clk *clk_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (i = 0; i < SPRD_PWM_CHN_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct sprd_pwm_chn *chn = &spc->chn[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) chn->clks[j].id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) chn->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return dev_err_probe(spc->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "failed to get channel clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) chn->clk_rate = clk_get_rate(clk_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(spc->dev, "no available PWM channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) spc->num_pwms = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int sprd_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct sprd_pwm_chip *spc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!spc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (IS_ERR(spc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return PTR_ERR(spc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) platform_set_drvdata(pdev, spc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = sprd_pwm_clk_init(spc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) spc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spc->chip.ops = &sprd_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spc->chip.npwm = spc->num_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = pwmchip_add(&spc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(&pdev->dev, "failed to add PWM chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int sprd_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct sprd_pwm_chip *spc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return pwmchip_remove(&spc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct of_device_id sprd_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { .compatible = "sprd,ums512-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DEVICE_TABLE(of, sprd_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct platform_driver sprd_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .name = "sprd-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .of_match_table = sprd_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .probe = sprd_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .remove = sprd_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) module_platform_driver(sprd_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DESCRIPTION("Spreadtrum PWM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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