^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * ST Microelectronics SPEAr Pulse Width Modulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NUM_PWM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* PWM registers and bits definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PWMCR 0x00 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PWMCR_PWM_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PWMCR_PRESCALE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PWMCR_MIN_PRESCALE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PWMCR_MAX_PRESCALE 0x3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PWMDCR 0x04 /* Duty Cycle Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PWMDCR_MIN_DUTY 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PWMDCR_MAX_DUTY 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PWMPCR 0x08 /* Period Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PWMPCR_MIN_PERIOD 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PWMPCR_MAX_PERIOD 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Following only available on 13xx SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PWMMCR 0x3C /* Master Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWMMCR_PWM_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * struct spear_pwm_chip - struct representing pwm chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @mmio_base: base address of pwm chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @clk: pointer to clk structure of pwm chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @chip: linux pwm chip representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct spear_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline struct spear_pwm_chip *to_spear_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return container_of(chip, struct spear_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline u32 spear_pwm_readl(struct spear_pwm_chip *chip, unsigned int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return readl_relaxed(chip->mmio_base + (num << 4) + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline void spear_pwm_writel(struct spear_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int num, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel_relaxed(val, chip->mmio_base + (num << 4) + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int spear_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct spear_pwm_chip *pc = to_spear_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u64 val, div, clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * according to formulas described below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * period_ns = 10^9 * (PRESCALE + 1) * PV / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clk_rate = clk_get_rate(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) div = 1000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) div *= 1 + prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val = clk_rate * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pv = div64_u64(val, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val = clk_rate * duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dc = div64_u64(val, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* if duty_ns and period_ns are not achievable then return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * if pv and dc have crossed their upper limit, then increase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * prescale and recalculate pv and dc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (++prescale > PWMCR_MAX_PRESCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * NOTE: the clock to PWM has to be enabled first before writing to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = clk_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spear_pwm_writel(pc, pwm->hwpwm, PWMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) prescale << PWMCR_PRESCALE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk_disable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int spear_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct spear_pwm_chip *pc = to_spear_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rc = clk_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val |= PWMCR_PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void spear_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct spear_pwm_chip *pc = to_spear_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val &= ~PWMCR_PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clk_disable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct pwm_ops spear_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .config = spear_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .enable = spear_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .disable = spear_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int spear_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct spear_pwm_chip *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (IS_ERR(pc->mmio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return PTR_ERR(pc->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pc->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (IS_ERR(pc->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return PTR_ERR(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pc->chip.ops = &spear_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pc->chip.npwm = NUM_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = clk_prepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (of_device_is_compatible(np, "st,spear1340-pwm")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = clk_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clk_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Following enables PWM chip, channels would still be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * enabled individually through their control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = readl_relaxed(pc->mmio_base + PWMMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val |= PWMMCR_PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel_relaxed(val, pc->mmio_base + PWMMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clk_disable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = pwmchip_add(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) clk_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int spear_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct spear_pwm_chip *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* clk was prepared in probe, hence unprepare it here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct of_device_id spear_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .compatible = "st,spear320-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .compatible = "st,spear1340-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_DEVICE_TABLE(of, spear_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct platform_driver spear_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "spear-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .of_match_table = spear_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .probe = spear_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .remove = spear_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) module_platform_driver(spear_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_AUTHOR("Shiraz Hashim <shiraz.linux.kernel@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MODULE_ALIAS("platform:spear-pwm");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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