Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * sl28cpld PWM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2020 Michael Walle <michael@walle.cc>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * There is no public datasheet available for this PWM core. But it is easy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * enough to be briefly explained. It consists of one 8-bit counter. The PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * supports four distinct frequencies by selecting when to reset the counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * With the prescaler setting you can select which bit of the counter is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * to reset it. This implies that the higher the frequency the less remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * bits are available for the actual counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Let cnt[7:0] be the counter, clocked at 32kHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * +-----------+--------+--------------+-----------+---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * | prescaler |  reset | counter bits | frequency | period length |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * +-----------+--------+--------------+-----------+---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * |         0 | cnt[7] |     cnt[6:0] |    250 Hz |    4000000 ns |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * |         1 | cnt[6] |     cnt[5:0] |    500 Hz |    2000000 ns |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * |         2 | cnt[5] |     cnt[4:0] |     1 kHz |    1000000 ns |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * |         3 | cnt[4] |     cnt[3:0] |     2 kHz |     500000 ns |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * +-----------+--------+--------------+-----------+---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * - The hardware cannot atomically set the prescaler and the counter value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *   which might lead to glitches and inconsistent states if a write fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * - The counter is not reset if you switch the prescaler which leads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *   to glitches, too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * - The duty cycle will switch immediately and not after a complete cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * - Depending on the actual implementation, disabling the PWM might have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *   side effects. For example, if the output pin is shared with a GPIO pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *   it will automatically switch back to GPIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * PWM timer block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SL28CPLD_PWM_CTRL			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define   SL28CPLD_PWM_CTRL_ENABLE		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define   SL28CPLD_PWM_CTRL_PRESCALER_MASK	GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SL28CPLD_PWM_CYCLE			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define   SL28CPLD_PWM_CYCLE_MAX		GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SL28CPLD_PWM_CLK			32000 /* 32 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)	(1 << (7 - (prescaler)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SL28CPLD_PWM_PERIOD(prescaler) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	(NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * We calculate the duty cycle like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  *   duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * With
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *   max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *   max_duty_cycle = 1 << (7 - prescaler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * this then simplifies to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *   duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *                 = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * precision by doing the divison first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	(NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	(DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define sl28cpld_pwm_read(priv, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define sl28cpld_pwm_write(priv, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) struct sl28cpld_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct pwm_chip pwm_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define sl28cpld_pwm_from_chip(_chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	container_of(_chip, struct sl28cpld_pwm, pwm_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void sl28cpld_pwm_get_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				   struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 				   struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	state->period = SL28CPLD_PWM_PERIOD(prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 * Sanitize values for the PWM core. Depending on the prescaler it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * might happen that we calculate a duty_cycle greater than the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * period. This might happen if someone (e.g. the bootloader) sets an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * invalid combination of values. The behavior of the hardware is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 * undefined in this case. But we need to report sane values back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 * the PWM core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	state->duty_cycle = min(state->duty_cycle, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			      const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	unsigned int cycle, prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	bool write_duty_cycle_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* Polarity inversion is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (state->polarity != PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 * Calculate the prescaler. Pick the biggest period that isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * bigger than the requested period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	prescaler = order_base_2(prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		ctrl |= SL28CPLD_PWM_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * Work around the hardware limitation. See also above. Trap 100% duty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * care about the frequency because its "all-one" in either case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * We don't need to check the actual prescaler setting, because only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * if the prescaler is 0 we can have this particular value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		ctrl |= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * To avoid glitches when we switch the prescaler, we have to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * we have a valid duty cycle for the new mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 * Take the current prescaler (or the current period length) into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	 * account to decide whether we have to write the duty cycle or the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 * prescaler first. If the period length is decreasing we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * write the duty cycle first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	write_duty_cycle_first = pwm->state.period > state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (write_duty_cycle_first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!write_duty_cycle_first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct pwm_ops sl28cpld_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.apply = sl28cpld_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.get_state = sl28cpld_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int sl28cpld_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct sl28cpld_pwm *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct pwm_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!pdev->dev.parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		dev_err(&pdev->dev, "no parent device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (!priv->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		dev_err(&pdev->dev, "could not get parent regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			ERR_PTR(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* Initialize the pwm_chip structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	chip = &priv->pwm_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	chip->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	chip->ops = &sl28cpld_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	chip->npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ret = pwmchip_add(&priv->pwm_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		dev_err(&pdev->dev, "failed to add PWM chip (%pe)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			ERR_PTR(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int sl28cpld_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct sl28cpld_pwm *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return pwmchip_remove(&priv->pwm_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct of_device_id sl28cpld_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	{ .compatible = "kontron,sl28cpld-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct platform_driver sl28cpld_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.probe = sl28cpld_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.remove	= sl28cpld_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.name = "sl28cpld-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.of_match_table = sl28cpld_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) module_platform_driver(sl28cpld_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_DESCRIPTION("sl28cpld PWM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_LICENSE("GPL");