Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017-2018 SiFive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * For SiFive's PWM IP block documentation please refer Chapter 14 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * - When changing both duty cycle and period, we cannot prevent in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *   software that the output might produce a period with mixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *   settings (new period length and old duty cycle).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * - The hardware cannot generate a 100% duty cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * - The hardware generates only inverted output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PWM_SIFIVE_PWMCFG		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PWM_SIFIVE_PWMCOUNT		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PWM_SIFIVE_PWMS			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PWM_SIFIVE_PWMCMP0		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* PWMCFG fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PWM_SIFIVE_PWMCFG_SCALE		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PWM_SIFIVE_PWMCFG_STICKY	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PWM_SIFIVE_PWMCFG_ZERO_CMP	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PWM_SIFIVE_PWMCFG_DEGLITCH	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PWM_SIFIVE_PWMCFG_EN_ALWAYS	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PWM_SIFIVE_PWMCFG_EN_ONCE	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PWM_SIFIVE_PWMCFG_CENTER	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PWM_SIFIVE_PWMCFG_GANG		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PWM_SIFIVE_PWMCFG_IP		BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PWM_SIFIVE_SIZE_PWMCMP		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PWM_SIFIVE_CMPWIDTH		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PWM_SIFIVE_DEFAULT_PERIOD	10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct pwm_sifive_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct pwm_chip	chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct mutex lock; /* lock to protect user_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct notifier_block notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned int real_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned int approx_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int user_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return container_of(c, struct pwm_sifive_ddata, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	mutex_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ddata->user_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	mutex_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mutex_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ddata->user_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	mutex_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				    unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	unsigned long long num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned long scale_pow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * period length is using pwmscale which provides the number of bits the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * counter is shifted before being feed to the comparators. A period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	      FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* As scale <= 15 the shift operation cannot overflow. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ddata->real_period = div64_ul(num, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	dev_dbg(ddata->chip.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		"New real_period = %u ns\n", ddata->real_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				 struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 duty, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		     pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	state->enabled = duty > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	state->period = ddata->real_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	state->duty_cycle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		(u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	state->polarity = PWM_POLARITY_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int pwm_sifive_enable(struct pwm_chip *chip, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		ret = clk_enable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			dev_err(ddata->chip.dev, "Enable clk failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		clk_disable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			    const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct pwm_state cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned int duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned long long num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32 frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (state->polarity != PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ret = clk_enable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		dev_err(ddata->chip.dev, "Enable clk failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	mutex_lock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	cur_state = pwm->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	enabled = cur_state.enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	duty_cycle = state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		duty_cycle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * The problem of output producing mixed setting as mentioned at top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * occurs here. To minimize the window for this problem, we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * calculating the register values first and then writing them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * consecutively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* The hardware cannot generate a 100% duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (state->period != ddata->approx_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		if (ddata->user_count != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		ddata->approx_period = state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	       pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (state->enabled != enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		pwm_sifive_enable(chip, state->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	clk_disable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	mutex_unlock(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct pwm_ops pwm_sifive_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.request = pwm_sifive_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.free = pwm_sifive_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.get_state = pwm_sifive_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.apply = pwm_sifive_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int pwm_sifive_clock_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				     unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct pwm_sifive_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		container_of(nb, struct pwm_sifive_ddata, notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (event == POST_RATE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		pwm_sifive_update_clock(ddata, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int pwm_sifive_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct pwm_sifive_ddata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct pwm_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mutex_init(&ddata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	chip = &ddata->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	chip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	chip->ops = &pwm_sifive_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	chip->of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	chip->of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	chip->npwm = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ddata->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (IS_ERR(ddata->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return PTR_ERR(ddata->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ddata->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (IS_ERR(ddata->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return dev_err_probe(dev, PTR_ERR(ddata->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				     "Unable to find controller clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ret = clk_prepare_enable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* Watch for changes to underlying clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ret = clk_notifier_register(ddata->clk, &ddata->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		dev_err(dev, "failed to register clock notifier: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ret = pwmchip_add(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		dev_err(dev, "cannot register PWM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		goto unregister_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	platform_set_drvdata(pdev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unregister_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	clk_notifier_unregister(ddata->clk, &ddata->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	clk_disable_unprepare(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int pwm_sifive_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	bool is_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct pwm_device *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int ret, ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	for (ch = 0; ch < ddata->chip.npwm; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		pwm = &ddata->chip.pwms[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		if (pwm->state.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			is_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		clk_disable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	clk_disable_unprepare(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	ret = pwmchip_remove(&ddata->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	clk_notifier_unregister(ddata->clk, &ddata->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct of_device_id pwm_sifive_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	{ .compatible = "sifive,pwm0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct platform_driver pwm_sifive_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.probe = pwm_sifive_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.remove = pwm_sifive_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.name = "pwm-sifive",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.of_match_table = pwm_sifive_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) module_platform_driver(pwm_sifive_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_DESCRIPTION("SiFive PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_LICENSE("GPL v2");