^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2007 Ben Dooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2017 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * PWM driver for Samsung SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* For struct samsung_timer_variant and samsung_pwm_lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <clocksource/samsung_pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_TCFG0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_TCFG1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_TCON 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TCFG0_PRESCALER_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TCFG0_PRESCALER1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TCFG1_MUX_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TCFG1_SHIFT(chan) (4 * (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Each channel occupies 4 bits in TCON register, but there is a gap of 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * bits (one channel) after channel 0, so channels have different numbering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * when accessing TCON register. See to_tcon_channel() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * in its set of bits is 2 as opposed to 3 for other channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TCON_START(chan) BIT(4 * (chan) + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TCON_INVERT(chan) BIT(4 * (chan) + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TCON_AUTORELOAD(chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * struct samsung_pwm_channel - private data of PWM channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @period_ns: current period in nanoseconds programmed to the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @duty_ns: current duty time in nanoseconds programmed to the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @tin_ns: time of one timer tick in nanoseconds with current timer rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct samsung_pwm_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 tin_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * struct samsung_pwm_chip - private data of PWM chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @chip: generic PWM chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @variant: local copy of hardware variant data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @inverter_mask: inverter status for all channels - one bit per channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @disabled_mask: disabled status for all channels - one bit per channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @base: base address of mapped PWM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @base_clk: base clock used to drive the timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @tclk0: external clock 0 (can be ERR_PTR if not present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @tclk1: external clock 1 (can be ERR_PTR if not present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct samsung_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct samsung_pwm_variant variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 inverter_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 disabled_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk *base_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk *tclk0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clk *tclk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #ifndef CONFIG_CLKSRC_SAMSUNG_PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * and some registers need access synchronization. If both drivers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * compiled in, the spinlock is defined in the clocksource driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * otherwise following definition is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Currently we do not need any more complex synchronization method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * because all the supported SoCs contain only one instance of the PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * IP. Should this change, both drivers will need to be modified to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * properly synchronize accesses to particular instances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static DEFINE_SPINLOCK(samsung_pwm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return container_of(chip, struct samsung_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline unsigned int to_tcon_channel(unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return (channel == 0) ? 0 : (channel + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int channel, u8 divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 shift = TCFG1_SHIFT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bits = (fls(divisor) - 1) - pwm->variant.div_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spin_lock_irqsave(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg = readl(pwm->base + REG_TCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg &= ~(TCFG1_MUX_MASK << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg |= bits << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(reg, pwm->base + REG_TCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) spin_unlock_irqrestore(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct samsung_pwm_variant *variant = &chip->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reg = readl(chip->base + REG_TCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg >>= TCFG1_SHIFT(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg &= TCFG1_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return (BIT(reg) & variant->tclk_mask) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rate = clk_get_rate(chip->base_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) reg = readl(chip->base + REG_TCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (chan >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) reg >>= TCFG0_PRESCALER1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) reg &= TCFG0_PRESCALER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return rate / (reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int chan, unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct samsung_pwm_variant *variant = &chip->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!pwm_samsung_is_tdiv(chip, chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clk = (chan < 2) ? chip->tclk0 : chip->tclk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_warn(chip->chip.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "tclk of PWM %d is inoperational, using tdiv\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rate = pwm_samsung_get_tin_rate(chip, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Compare minimum PWM frequency that can be achieved with possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * divider settings and choose the lowest divisor that can generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * frequencies lower than requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (variant->bits < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Only for s3c24xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (div = variant->div_base; div < 4; ++div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if ((rate >> (variant->bits + div)) < freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Other variants have enough counter bits to generate any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * requested rate, so no need to check higher divisors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) div = variant->div_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pwm_samsung_set_divisor(chip, chan, BIT(div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return rate >> div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct samsung_pwm_channel *our_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_warn(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "tried to request PWM channel %d without output\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) our_chan = kzalloc(sizeof(*our_chan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!our_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pwm_set_chip_data(pwm, our_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) kfree(pwm_get_chip_data(pwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 tcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) spin_lock_irqsave(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tcon = readl(our_chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tcon &= ~TCON_START(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tcon |= TCON_MANUALUPDATE(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(tcon, our_chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tcon &= ~TCON_MANUALUPDATE(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel(tcon, our_chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) our_chip->disabled_mask &= ~BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) spin_unlock_irqrestore(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 tcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_lock_irqsave(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) tcon = readl(our_chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tcon &= ~TCON_AUTORELOAD(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(tcon, our_chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) our_chip->disabled_mask |= BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) spin_unlock_irqrestore(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 tcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) spin_lock_irqsave(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tcon = readl(chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tcon |= TCON_MANUALUPDATE(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel(tcon, chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tcon &= ~TCON_MANUALUPDATE(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) writel(tcon, chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spin_unlock_irqrestore(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int duty_ns, int period_ns, bool force_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * We currently avoid using 64bit arithmetic by using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * fact that anything faster than 1Hz is easily representable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * by 32bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (period_ns > NSEC_PER_SEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* We need tick count for calculation, not last tick. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ++tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Check to see if we are changing the clock rate of the PWM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (chan->period_ns != period_ns || force_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long tin_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) period = NSEC_PER_SEC / period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) duty_ns, period_ns, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) tin_ns = NSEC_PER_SEC / tin_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) tcnt = period_ns / tin_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Period is too short. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (tcnt <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Note that counters count down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tcmp = duty_ns / tin_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* 0% duty is not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!tcmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ++tcmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tcmp = tcnt - tcmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Decrement to get tick numbers, instead of tick counts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) --tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* -1UL will give 100% duty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) --tcmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_dbg(our_chip->chip.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Update PWM registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * In case the PWM is currently at 100% duty cycle, force a manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * update to prevent the signal staying high if the PWM is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * shortly afer this update (before it autoreloaded the new values).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (oldtcmp == (u32) -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_dbg(our_chip->chip.dev, "Forcing manual update");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pwm_samsung_manual_update(our_chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) chan->period_ns = period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) chan->tin_ns = tin_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) chan->duty_ns = duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int channel, bool invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int tcon_chan = to_tcon_channel(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 tcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) spin_lock_irqsave(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tcon = readl(chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (invert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) chip->inverter_mask |= BIT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tcon |= TCON_INVERT(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) chip->inverter_mask &= ~BIT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tcon &= ~TCON_INVERT(tcon_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writel(tcon, chip->base + REG_TCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) spin_unlock_irqrestore(&samsung_pwm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int pwm_samsung_set_polarity(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) bool invert = (polarity == PWM_POLARITY_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Inverted means normal in the hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct pwm_ops pwm_samsung_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .request = pwm_samsung_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .free = pwm_samsung_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .enable = pwm_samsung_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .disable = pwm_samsung_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .config = pwm_samsung_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .set_polarity = pwm_samsung_set_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct samsung_pwm_variant s3c24xx_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .div_base = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .has_tint_cstat = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .tclk_mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct samsung_pwm_variant s3c64xx_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .div_base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .has_tint_cstat = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .tclk_mask = BIT(7) | BIT(6) | BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct samsung_pwm_variant s5p64x0_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .div_base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .has_tint_cstat = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .tclk_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct samsung_pwm_variant s5pc100_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .div_base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .has_tint_cstat = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .tclk_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const struct of_device_id samsung_pwm_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct device_node *np = chip->chip.dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const __be32 *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) match = of_match_node(samsung_pwm_matches, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) memcpy(&chip->variant, match->data, sizeof(chip->variant));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (val >= SAMSUNG_PWM_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(chip->chip.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "%s: invalid channel index in samsung,pwm-outputs property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) chip->variant.output_mask |= BIT(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int pwm_samsung_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct samsung_pwm_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned int chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) chip->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) chip->chip.ops = &pwm_samsung_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) chip->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) chip->chip.npwm = SAMSUNG_PWM_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = pwm_samsung_parse_dt(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) chip->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) chip->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!pdev->dev.platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_err(&pdev->dev, "no platform data specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) memcpy(&chip->variant, pdev->dev.platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) sizeof(chip->variant));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) chip->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (IS_ERR(chip->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return PTR_ERR(chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) chip->base_clk = devm_clk_get(&pdev->dev, "timers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (IS_ERR(chip->base_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(dev, "failed to get timer base clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return PTR_ERR(chip->base_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = clk_prepare_enable(chip->base_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(dev, "failed to enable base clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (chip->variant.output_mask & BIT(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pwm_samsung_set_invert(chip, chan, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Following clocks are optional. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = pwmchip_add(&chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(dev, "failed to register PWM chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk_disable_unprepare(chip->base_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) clk_get_rate(chip->base_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int pwm_samsung_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct samsung_pwm_chip *chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = pwmchip_remove(&chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) clk_disable_unprepare(chip->base_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int pwm_samsung_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct pwm_chip *chip = &our_chip->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) for (i = 0; i < SAMSUNG_PWM_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct pwm_device *pwm = &chip->pwms[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (our_chip->variant.output_mask & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pwm_samsung_set_invert(our_chip, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) our_chip->inverter_mask & BIT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (chan->period_ns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) __pwm_samsung_config(chip, pwm, chan->duty_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) chan->period_ns, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* needed to make PWM disable work on Odroid-XU3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pwm_samsung_manual_update(our_chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (our_chip->disabled_mask & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pwm_samsung_disable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pwm_samsung_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static struct platform_driver pwm_samsung_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .name = "samsung-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .pm = &pwm_samsung_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .of_match_table = of_match_ptr(samsung_pwm_matches),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .probe = pwm_samsung_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .remove = pwm_samsung_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) module_platform_driver(pwm_samsung_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MODULE_ALIAS("platform:samsung-pwm");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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