Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PWM driver for Rockchip SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2014 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PWM_CTRL_TIMER_EN	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PWM_CTRL_OUTPUT_EN	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PWM_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PWM_CONTINUOUS		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PWM_DUTY_POSITIVE	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PWM_DUTY_NEGATIVE	(0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PWM_INACTIVE_NEGATIVE	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PWM_INACTIVE_POSITIVE	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PWM_POLARITY_MASK	(PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PWM_OUTPUT_LEFT		(0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PWM_OUTPUT_CENTER	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PWM_LOCK_EN		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PWM_LP_DISABLE		(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PWM_ONESHOT_COUNT_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PWM_ONESHOT_COUNT_MAX	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct rockchip_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct pinctrl_state *active_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	const struct rockchip_pwm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	bool vop_pwm_en; /* indicate voppwm mirror register state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	bool center_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	bool oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct rockchip_pwm_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned long period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned long cntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned long ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) struct rockchip_pwm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct rockchip_pwm_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned int prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	bool supports_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	bool supports_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	bool vop_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u32 enable_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 enable_conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return container_of(c, struct rockchip_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void rockchip_pwm_get_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				   struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				   struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 enable_conf = pc->data->enable_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ret = clk_enable(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	tmp = readl_relaxed(pc->base + pc->data->regs.period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	tmp *= pc->data->prescaler * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	tmp *= pc->data->prescaler * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	state->enabled = (val & enable_conf) == enable_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		state->polarity = PWM_POLARITY_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	clk_disable(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			       const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long period, duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u64 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * Since period and duty cycle registers have a width of 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * bits, every possible input period can be obtained using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * default prescaler value for all practical clock rate values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	div = (u64)pc->clk_rate * state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	period = DIV_ROUND_CLOSEST_ULL(div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				       pc->data->prescaler * NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	div = (u64)pc->clk_rate * state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * Lock the period and duty of previous configuration, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * change the duty and period, that would not be effective.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (pc->data->vop_pwm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		if (pc->vop_pwm_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			ctrl |= PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			ctrl &= ~PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_PWM_ROCKCHIP_ONESHOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (state->oneshot_count > PWM_ONESHOT_COUNT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		pc->oneshot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		dev_err(chip->dev, "Oneshot_count value overflow.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	} else if (state->oneshot_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		pc->oneshot = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		ctrl |= (state->oneshot_count - 1) << PWM_ONESHOT_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		pc->oneshot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		ctrl |= PWM_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (pc->data->supports_lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		ctrl |= PWM_LOCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	writel(period, pc->base + pc->data->regs.period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	writel(duty, pc->base + pc->data->regs.duty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (pc->data->supports_polarity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		ctrl &= ~PWM_POLARITY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (state->polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 * Unlock and set polarity at the same time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * the configuration of duty, period and polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * would be effective together at next period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (pc->data->supports_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		ctrl &= ~PWM_LOCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	writel(ctrl, pc->base + pc->data->regs.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int rockchip_pwm_enable(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			       struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			       bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u32 enable_conf = pc->data->enable_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		ret = clk_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	val &= ~pc->data->enable_conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (PWM_OUTPUT_CENTER & pc->data->enable_conf_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		if (pc->center_aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			val |= PWM_OUTPUT_CENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		val |= enable_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		if (pc->oneshot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			val &= ~PWM_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		val &= ~enable_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (pc->data->vop_pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		pc->vop_pwm_en = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		clk_disable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			      const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct pwm_state curstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ret = clk_enable(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	pwm_get_state(pwm, &curstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	enabled = curstate.enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (state->polarity != curstate.polarity && enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	    !pc->data->supports_lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		ret = rockchip_pwm_enable(chip, pwm, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	rockchip_pwm_config(chip, pwm, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (state->enabled != enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		ret = rockchip_pwm_enable(chip, pwm, state->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		ret = pinctrl_select_state(pc->pinctrl, pc->active_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	clk_disable(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct pwm_ops rockchip_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.get_state = rockchip_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.apply = rockchip_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct rockchip_pwm_data pwm_data_v1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.duty = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.period = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.cntr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.ctrl = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.prescaler = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.supports_polarity = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.supports_lock = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.vop_pwm = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.enable_conf_mask = BIT(1) | BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct rockchip_pwm_data pwm_data_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.duty = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.period = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.cntr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.ctrl = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.prescaler = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.supports_polarity = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.supports_lock = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.vop_pwm = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		       PWM_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct rockchip_pwm_data pwm_data_vop = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.duty = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.period = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.cntr = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.ctrl = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.prescaler = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.supports_polarity = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.supports_lock = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.vop_pwm = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		       PWM_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct rockchip_pwm_data pwm_data_v3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.duty = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.period = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.cntr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.ctrl = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.prescaler = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.supports_polarity = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.supports_lock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.vop_pwm = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		       PWM_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct of_device_id rockchip_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int rockchip_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct rockchip_pwm_chip *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	u32 enable_conf, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	int ret, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	pc->base = devm_ioremap(&pdev->dev, r->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (IS_ERR(pc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return PTR_ERR(pc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	pc->clk = devm_clk_get(&pdev->dev, "pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (IS_ERR(pc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		pc->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (IS_ERR(pc->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 					     "Can't get bus clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	count = of_count_phandle_with_args(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 					   "clocks", "#clock-cells");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (count == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		pc->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		pc->pclk = pc->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (IS_ERR(pc->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		ret = PTR_ERR(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	ret = clk_prepare_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ret = clk_prepare_enable(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		dev_err(&pdev->dev, "Can't prepare enable APB clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	pc->pinctrl = devm_pinctrl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (IS_ERR(pc->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		dev_err(&pdev->dev, "Get pinctrl failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		return PTR_ERR(pc->pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	pc->active_state = pinctrl_lookup_state(pc->pinctrl, "active");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (IS_ERR(pc->active_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		dev_err(&pdev->dev, "No active pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		return PTR_ERR(pc->active_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	pc->data = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	pc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	pc->chip.ops = &rockchip_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	pc->chip.base = of_alias_get_id(pdev->dev.of_node, "pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	pc->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	pc->clk_rate = clk_get_rate(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (pc->data->supports_polarity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		pc->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		pc->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	enable_conf = pc->data->enable_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	enabled = (ctrl & enable_conf) == enable_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	pc->center_aligned =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		device_property_read_bool(&pdev->dev, "center-aligned");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	ret = pwmchip_add(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		goto err_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	if (!enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		clk_disable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	clk_disable(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) err_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	clk_disable_unprepare(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	clk_disable_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int rockchip_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	clk_unprepare(pc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	clk_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct platform_driver rockchip_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		.name = "rockchip-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		.of_match_table = rockchip_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	.probe = rockchip_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	.remove = rockchip_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int __init rockchip_pwm_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	return platform_driver_register(&rockchip_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) subsys_initcall(rockchip_pwm_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void __exit rockchip_pwm_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	platform_driver_unregister(&rockchip_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) module_exit(rockchip_pwm_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) module_platform_driver(rockchip_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MODULE_DESCRIPTION("Rockchip SoC PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MODULE_LICENSE("GPL v2");