^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * PWM-I2S driver for Rockchip SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* transmit operation control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2S_TXCR_FBM_MSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2S_TXCR_FBM_LSB BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2S_TXCR_IBM_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2S_TXCR_IBM_LSJM BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2S_TXCR_IBM_RSJM BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2S_TXCR_IBM_MASK GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2S_TXCR_VDW(x) ((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2S_TXCR_VDW_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* clock generation register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2S_CKR_TSD(x) ((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2S_CKR_TSD_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* DMA control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2S_DMACR_TDE_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2S_DMACR_TDE_ENABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2S_DMACR_TDL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2S_DMACR_TDL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Transfer start register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2S_XFER_TXS_STOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2S_XFER_TXS_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* clear SCLK domain logic register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2S_CLR_TXC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Mclk div register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2S_CLKDIV_TXM(x) ((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* I2S REGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2S_TXCR (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2S_RXCR (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2S_CKR (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2S_FIFOLR (0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2S_DMACR (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2S_INTCR (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2S_INTSR (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2S_XFER (0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2S_CLR (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2S_TXDR (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2S_RXDR (0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2S_TDM_TXCR (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2S_TDM_RXCR (0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2S_CLKDIV (0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Hardware Param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2S_FORMAT_BITS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2S_CHANNEL_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2S_FRAME_BITS (I2S_FORMAT_BITS * I2S_CHANNEL_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2S_FRAME_BYTES (I2S_FRAME_BITS / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I2S_FIFO_WATERMARK_LEVEL 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2S_DMA_BUFFER_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I2S_DMA_BUFFER_FRAME_SIZE (I2S_DMA_BUFFER_SIZE / I2S_FRAME_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct rockchip_i2s_pwm_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct dma_chan *chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dma_addr_t tx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) char *tx_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dma_cookie_t tx_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct rockchip_i2s_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct rockchip_i2s_pwm_dma dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct rockchip_i2s_pwm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pwm_state pwm_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct rockchip_i2s_pwm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int reg_clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int bit_clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int mask_clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct rockchip_i2s_pwm_chip *to_rockchip_i2s_pwm_chip(struct pwm_chip *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return container_of(c, struct rockchip_i2s_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void rockchip_i2s_pwm_get_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct rockchip_i2s_pwm_chip *pc = to_rockchip_i2s_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = clk_enable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) memcpy(state, &pc->pwm_state, sizeof(struct pwm_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ctrl = readl_relaxed(pc->base + I2S_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ctrl & I2S_XFER_TXS_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clk_disable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int rockchip_i2s_pwm_config(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct rockchip_i2s_pwm_chip *pc = to_rockchip_i2s_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long div_bclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u64 mclk_rate, period_div, duty, duty_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = clk_enable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Assume the time of a frame is a period of pwm, so a frame is the unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * of the pwm, we have to config the buffer per frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mclk_rate = clk_get_rate(pc->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) period_div = mclk_rate * state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) div_bclk = DIV_ROUND_CLOSEST(period_div, I2S_FRAME_BITS * NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * The duty pecent is equal to the bits percent at whole frame, as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * time of a frame is a period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) duty_div = DIV_ROUND_CLOSEST(I2S_FRAME_BITS * state->duty_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (duty_div > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) duty = GENMASK_ULL(duty_div - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) duty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (state->polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) duty = ~duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) div_val = readl_relaxed(pc->base + pc->data->reg_clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) div_val &= ~pc->data->mask_clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel_relaxed((I2S_CLKDIV_TXM(div_bclk) << pc->data->bit_clkdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) | div_val, pc->base + pc->data->reg_clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (i = 0; i < I2S_DMA_BUFFER_FRAME_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) memcpy((u64 *)pc->dma.tx_buff + i, &duty, sizeof(u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pc->pwm_state.period = state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pc->pwm_state.duty_cycle = state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pc->pwm_state.polarity = state->polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clk_disable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int rockchip_i2s_pwm_enable(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct rockchip_i2s_pwm_chip *pc = to_rockchip_i2s_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct rockchip_i2s_pwm_dma *dma = &pc->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct dma_async_tx_descriptor *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret, retry = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = clk_enable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = clk_enable(pc->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto err_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) tx_desc = dmaengine_prep_dma_cyclic(dma->chan_tx, dma->tx_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) I2S_DMA_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) I2S_DMA_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!tx_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(chip->dev, "Not able to get tx desc for DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tx_desc->callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tx_desc->callback_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dma->tx_cookie = dmaengine_submit(tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = dma_submit_error(dma->tx_cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(chip->dev, "DMA submit failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dma_async_issue_pending(pc->dma.chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val = readl_relaxed(pc->base + I2S_DMACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val &= ~I2S_DMACR_TDE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel_relaxed(val | I2S_DMACR_TDE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pc->base + I2S_DMACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val = readl_relaxed(pc->base + I2S_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val &= ~I2S_XFER_TXS_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writel_relaxed(val | I2S_XFER_TXS_START, pc->base + I2S_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dmaengine_terminate_all(pc->dma.chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val = readl_relaxed(pc->base + I2S_DMACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val &= ~I2S_DMACR_TDE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel_relaxed(val | I2S_DMACR_TDE_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pc->base + I2S_DMACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val = readl_relaxed(pc->base + I2S_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val &= ~I2S_XFER_TXS_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel_relaxed(val | I2S_XFER_TXS_STOP, pc->base + I2S_XFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val = readl_relaxed(pc->base + I2S_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) val &= ~I2S_CLR_TXC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writel_relaxed(val | I2S_CLR_TXC, pc->base + I2S_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Should wait for clear operation to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val = readl_relaxed(pc->base + I2S_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } while (--retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_warn(chip->dev, "fail to clear\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk_disable(pc->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk_disable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clk_disable(pc->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) err_mclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) clk_disable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int rockchip_i2s_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pwm_state curstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pwm_get_state(pwm, &curstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enabled = curstate.enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = rockchip_i2s_pwm_config(chip, pwm, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (state->enabled != enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = rockchip_i2s_pwm_enable(chip, pwm, state->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rockchip_i2s_pwm_get_state(chip, pwm, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct pwm_ops rockchip_i2s_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .get_state = rockchip_i2s_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .apply = rockchip_i2s_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int rockchip_i2s_pwm_dma_request(struct rockchip_i2s_pwm_chip *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dma_addr_t phy_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct rockchip_i2s_pwm_dma *dma = &pc->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct dma_slave_config dma_sconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) memset(&dma_sconfig, 0, sizeof(dma_sconfig));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dma->chan_tx = dma_request_slave_channel(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!dma->chan_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(dev, "can't request DMA tx channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dma_sconfig.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dma_sconfig.dst_addr = phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dma_sconfig.dst_maxburst = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(dev, "can't configure tx channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dma->tx_buff = dma_alloc_coherent(dev, I2S_DMA_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &dma->tx_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!dma->tx_buff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dma_release_channel(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static void rockchip_i2s_pwm_dma_release(struct rockchip_i2s_pwm_chip *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct rockchip_i2s_pwm_dma *dma = &pc->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct device *dev = pc->chip.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dma_free_coherent(dev, I2S_DMA_BUFFER_SIZE, dma->tx_buff, dma->tx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dma_release_channel(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int rockchip_i2s_pwm_hw_params(struct rockchip_i2s_pwm_chip *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = clk_enable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Config tx format bits with 32, LSB, left justified. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) val = readl_relaxed(pc->base + I2S_TXCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val &= ~(I2S_TXCR_VDW_MASK | I2S_TXCR_IBM_MASK | I2S_TXCR_FBM_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) writel_relaxed(val | I2S_TXCR_VDW(I2S_FORMAT_BITS) | I2S_TXCR_IBM_LSJM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) | I2S_TXCR_FBM_LSB, pc->base + I2S_TXCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) val = readl_relaxed(pc->base + I2S_CKR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val &= ~I2S_CKR_TSD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writel_relaxed(val | I2S_CKR_TSD(I2S_FRAME_BITS), pc->base + I2S_CKR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Config the tx fifo watermark level to 30. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val = readl_relaxed(pc->base + I2S_DMACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val &= ~I2S_DMACR_TDL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel_relaxed(val | I2S_DMACR_TDL(I2S_FIFO_WATERMARK_LEVEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pc->base + I2S_DMACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) clk_disable(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct rockchip_i2s_pwm_data i2s_pwm_data_v1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .reg_clkdiv = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .bit_clkdiv = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .mask_clkdiv = GENMASK(23, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct rockchip_i2s_pwm_data i2s_pwm_data_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .reg_clkdiv = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .bit_clkdiv = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .mask_clkdiv = GENMASK(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const struct of_device_id rockchip_i2s_pwm_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { .compatible = "rockchip,i2s-pwm", .data = &i2s_pwm_data_v1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { .compatible = "rockchip,rk3308-i2s-pwm", .data = &i2s_pwm_data_v2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int rockchip_i2s_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct rockchip_i2s_pwm_chip *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) id = of_match_device(rockchip_i2s_pwm_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pc->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (IS_ERR(pc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return PTR_ERR(pc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pc->hclk = devm_clk_get(&pdev->dev, "hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (IS_ERR(pc->hclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return PTR_ERR(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pc->mclk = devm_clk_get(&pdev->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (IS_ERR(pc->mclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return PTR_ERR(pc->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = clk_prepare(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = clk_prepare(pc->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) goto err_hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = rockchip_i2s_pwm_hw_params(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) goto err_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = rockchip_i2s_pwm_dma_request(pc, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) res->start + I2S_TXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto err_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pc->data = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pc->chip.ops = &rockchip_i2s_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pc->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pc->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pc->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = pwmchip_add(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) rockchip_i2s_pwm_dma_release(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto err_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) err_mclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clk_unprepare(pc->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) err_hclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) clk_unprepare(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int rockchip_i2s_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct rockchip_i2s_pwm_chip *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct pwm_state curstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pwm_get_state(pc->chip.pwms, &curstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (curstate.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dmaengine_terminate_all(pc->dma.chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) rockchip_i2s_pwm_dma_release(pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk_unprepare(pc->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) clk_unprepare(pc->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct platform_driver rockchip_i2s_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .name = "rockchip-i2s-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .of_match_table = rockchip_i2s_pwm_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .probe = rockchip_i2s_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .remove = rockchip_i2s_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) module_platform_driver(rockchip_i2s_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MODULE_AUTHOR("David Wu <david.wu@rock-chip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_DESCRIPTION("ROCKCHIP I2S PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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