Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * R-Car PWM Timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * - The hardware cannot generate a 0% duty cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RCAR_PWM_MAX_DIVISION	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RCAR_PWM_MAX_CYCLE	1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RCAR_PWMCR		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define  RCAR_PWMCR_CC0_MASK	0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define  RCAR_PWMCR_CC0_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define  RCAR_PWMCR_CCMD	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define  RCAR_PWMCR_SYNC	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define  RCAR_PWMCR_SS0		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define  RCAR_PWMCR_EN0		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RCAR_PWMCNT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define  RCAR_PWMCNT_CYC0_MASK	0x03ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define  RCAR_PWMCNT_CYC0_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define  RCAR_PWMCNT_PH0_MASK	0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define  RCAR_PWMCNT_PH0_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct rcar_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	return container_of(chip, struct rcar_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			   unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	writel(data, rp->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return readl(rp->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			    unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	value = rcar_pwm_read(rp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	value |= data & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	rcar_pwm_write(rp, value, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned long clk_rate = clk_get_rate(rp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u64 div, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (clk_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	tmp = (u64)period_ns * clk_rate + div - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	tmp = div64_u64(tmp, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	div = ilog2(tmp - 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				       unsigned int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	value = rcar_pwm_read(rp, RCAR_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (div & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		value |= RCAR_PWMCR_CCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	div >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	value |= div << RCAR_PWMCR_CC0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	rcar_pwm_write(rp, value, RCAR_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned long long one_cycle, tmp;	/* 0.01 nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long clk_rate = clk_get_rate(rp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u32 cyc, ph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	do_div(one_cycle, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	tmp = period_ns * 100ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	do_div(tmp, one_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	tmp = duty_ns * 100ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	do_div(tmp, one_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	ph = tmp & RCAR_PWMCNT_PH0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* Avoid prohibited setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (cyc == 0 || ph == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return pm_runtime_get_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	pm_runtime_put(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* Don't enable the PWM device if CYC0 or PH0 is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	value = rcar_pwm_read(rp, RCAR_PWMCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	    (value & RCAR_PWMCNT_PH0_MASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			  const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int div, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* This HW/driver only supports normal polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (state->polarity != PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		rcar_pwm_disable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	div = rcar_pwm_get_clock_division(rp, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		rcar_pwm_set_clock_control(rp, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		ret = rcar_pwm_enable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct pwm_ops rcar_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.request = rcar_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.free = rcar_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.apply = rcar_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int rcar_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct rcar_pwm_chip *rcar_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (rcar_pwm == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (IS_ERR(rcar_pwm->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return PTR_ERR(rcar_pwm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (IS_ERR(rcar_pwm->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		dev_err(&pdev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return PTR_ERR(rcar_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	platform_set_drvdata(pdev, rcar_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	rcar_pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	rcar_pwm->chip.ops = &rcar_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	rcar_pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	rcar_pwm->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ret = pwmchip_add(&rcar_pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int rcar_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret = pwmchip_remove(&rcar_pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct of_device_id rcar_pwm_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	{ .compatible = "renesas,pwm-rcar", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct platform_driver rcar_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.probe = rcar_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.remove = rcar_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.name = "pwm-rcar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.of_match_table = of_match_ptr(rcar_pwm_of_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) module_platform_driver(rcar_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_DESCRIPTION("Renesas PWM Timer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MODULE_ALIAS("platform:pwm-rcar");