^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/pwm/pwm-pxa.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * simple driver for PWM (Pulse Width Modulator) controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2008-02-13 initial version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * eric miao <eric.miao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HAS_SECONDARY_PWM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct platform_device_id pwm_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* PWM has_secondary_pwm? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { "pxa25x-pwm", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { "pxa27x-pwm", HAS_SECONDARY_PWM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { "pxa168-pwm", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { "pxa910-pwm", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_DEVICE_TABLE(platform, pwm_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* PWM registers and bits definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PWMCR (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PWMDCR (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PWMPCR (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PWMCR_SD (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PWMDCR_FD (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct pxa_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return container_of(chip, struct pxa_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long period_cycles, prescale, pv, dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) offset = pwm->hwpwm ? 0x10 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) c = clk_get_rate(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) c = c * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) do_div(c, 1000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) period_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (period_cycles < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) period_cycles = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) prescale = (period_cycles - 1) / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pv = period_cycles / (prescale + 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (prescale > 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (duty_ns == period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dc = PWMDCR_FD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dc = (pv + 1) * duty_ns / period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* NOTE: the clock to PWM has to be enabled first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * before writing to the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) rc = clk_prepare_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(prescale, pc->mmio_base + offset + PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel(dc, pc->mmio_base + offset + PWMDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(pv, pc->mmio_base + offset + PWMPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clk_disable_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return clk_prepare_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_disable_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct pwm_ops pxa_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .config = pxa_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .enable = pxa_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .disable = pxa_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Device tree users must create one device instance for each PWM channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Hence we dispense with the HAS_SECONDARY_PWM and "tell" the original driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * code that this is a single channel pxa25x-pwm. Currently all devices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * supported identically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct of_device_id pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .compatible = "marvell,pxa250-pwm", .data = &pwm_id_table[0]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0]},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MODULE_DEVICE_TABLE(of, pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define pwm_of_match NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct platform_device_id *pxa_pwm_get_id_dt(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct of_device_id *id = of_match_device(pwm_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return id ? id->data : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct pwm_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pxa_pwm_of_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct pwm_device *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pwm = pwm_request_from_chip(pc, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (IS_ERR(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pwm->args.period = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const struct platform_device_id *id = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pxa_pwm_chip *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (IS_ENABLED(CONFIG_OF) && id == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) id = pxa_pwm_get_id_dt(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (id == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (pwm == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pwm->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (IS_ERR(pwm->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return PTR_ERR(pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pwm->chip.ops = &pxa_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pwm->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (IS_ENABLED(CONFIG_OF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pwm->chip.of_xlate = pxa_pwm_of_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pwm->chip.of_pwm_n_cells = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (IS_ERR(pwm->mmio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return PTR_ERR(pwm->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = pwmchip_add(&pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) platform_set_drvdata(pdev, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct pxa_pwm_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return pwmchip_remove(&chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct platform_driver pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .name = "pxa25x-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .of_match_table = pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .probe = pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .remove = pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .id_table = pwm_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) module_platform_driver(pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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