^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for PCA9685 16-channel 12-bit PWM LED controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Clemens Gruber <clemens.gruber@pqgruber.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on the pwm-twl-led.c driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Because the PCA9685 has only one prescaler per chip, changing the period of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * one channel affects the period of all 16 PWM outputs!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * However, the ratio between each configured duty cycle and the chip-wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * period remains constant, because the OFF time is set in proportion to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * counter range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCA9685_MODE1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCA9685_MODE2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCA9685_SUBADDR1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCA9685_SUBADDR2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCA9685_SUBADDR3 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCA9685_ALLCALLADDR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCA9685_LEDX_ON_L 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCA9685_LEDX_ON_H 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCA9685_LEDX_OFF_L 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCA9685_LEDX_OFF_H 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCA9685_ALL_LED_ON_L 0xFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCA9685_ALL_LED_ON_H 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCA9685_ALL_LED_OFF_L 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCA9685_ALL_LED_OFF_H 0xFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCA9685_PRESCALE 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCA9685_PRESCALE_MIN 0x03 /* => max. frequency of 1526 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCA9685_PRESCALE_MAX 0xFF /* => min. frequency of 24 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCA9685_COUNTER_RANGE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCA9685_DEFAULT_PERIOD 5000000 /* Default period_ns = 1/200 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCA9685_OSC_CLOCK_MHZ 25 /* Internal oscillator with 25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCA9685_NUMREGS 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCA9685_MAXCHAN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LED_FULL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MODE1_ALLCALL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MODE1_SUB3 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MODE1_SUB2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MODE1_SUB1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MODE1_SLEEP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MODE2_INVRT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MODE2_OUTDRV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LED_N_ON_H(N) (PCA9685_LEDX_ON_H + (4 * (N)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LED_N_ON_L(N) (PCA9685_LEDX_ON_L + (4 * (N)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LED_N_OFF_H(N) (PCA9685_LEDX_OFF_H + (4 * (N)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LED_N_OFF_L(N) (PCA9685_LEDX_OFF_L + (4 * (N)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct pca9685 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #if IS_ENABLED(CONFIG_GPIOLIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DECLARE_BITMAP(pwms_inuse, PCA9685_MAXCHAN + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline struct pca9685 *to_pca(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return container_of(chip, struct pca9685, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #if IS_ENABLED(CONFIG_GPIOLIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static bool pca9685_pwm_test_and_set_inuse(struct pca9685 *pca, int pwm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool is_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mutex_lock(&pca->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (pwm_idx >= PCA9685_MAXCHAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * "All LEDs" channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * pretend already in use if any of the PWMs are requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!bitmap_empty(pca->pwms_inuse, PCA9685_MAXCHAN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) is_inuse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Regular channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * pretend already in use if the "all LEDs" channel is requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (test_bit(PCA9685_MAXCHAN, pca->pwms_inuse)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) is_inuse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) is_inuse = test_and_set_bit(pwm_idx, pca->pwms_inuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mutex_unlock(&pca->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return is_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void pca9685_pwm_clear_inuse(struct pca9685 *pca, int pwm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mutex_lock(&pca->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clear_bit(pwm_idx, pca->pwms_inuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mutex_unlock(&pca->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int pca9685_pwm_gpio_request(struct gpio_chip *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct pca9685 *pca = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (pca9685_pwm_test_and_set_inuse(pca, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pm_runtime_get_sync(pca->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int pca9685_pwm_gpio_get(struct gpio_chip *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct pca9685 *pca = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct pwm_device *pwm = &pca->chip.pwms[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) regmap_read(pca->regmap, LED_N_ON_H(pwm->hwpwm), &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return value & LED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void pca9685_pwm_gpio_set(struct gpio_chip *gpio, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct pca9685 *pca = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct pwm_device *pwm = &pca->chip.pwms[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int on = value ? LED_FULL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Clear both OFF registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) regmap_write(pca->regmap, LED_N_OFF_L(pwm->hwpwm), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regmap_write(pca->regmap, LED_N_OFF_H(pwm->hwpwm), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Set the full ON bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) regmap_write(pca->regmap, LED_N_ON_H(pwm->hwpwm), on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void pca9685_pwm_gpio_free(struct gpio_chip *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct pca9685 *pca = gpiochip_get_data(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pca9685_pwm_gpio_set(gpio, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pm_runtime_put(pca->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pca9685_pwm_clear_inuse(pca, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int pca9685_pwm_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Always out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int pca9685_pwm_gpio_direction_input(struct gpio_chip *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int pca9685_pwm_gpio_direction_output(struct gpio_chip *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pca9685_pwm_gpio_set(gpio, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * The PCA9685 has a bit for turning the PWM output full off or on. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * boards like Intel Galileo actually uses these as normal GPIOs so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * expose a GPIO chip here which can exclusively take over the underlying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * PWM channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int pca9685_pwm_gpio_probe(struct pca9685 *pca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct device *dev = pca->chip.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mutex_init(&pca->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pca->gpio.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pca->gpio.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pca->gpio.request = pca9685_pwm_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pca->gpio.free = pca9685_pwm_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pca->gpio.get_direction = pca9685_pwm_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pca->gpio.direction_input = pca9685_pwm_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pca->gpio.direction_output = pca9685_pwm_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pca->gpio.get = pca9685_pwm_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pca->gpio.set = pca9685_pwm_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pca->gpio.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pca->gpio.ngpio = PCA9685_MAXCHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pca->gpio.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return devm_gpiochip_add_data(dev, &pca->gpio, pca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline bool pca9685_pwm_test_and_set_inuse(struct pca9685 *pca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int pwm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pca9685_pwm_clear_inuse(struct pca9685 *pca, int pwm_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline int pca9685_pwm_gpio_probe(struct pca9685 *pca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void pca9685_set_sleep_mode(struct pca9685 *pca, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) regmap_update_bits(pca->regmap, PCA9685_MODE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODE1_SLEEP, enable ? MODE1_SLEEP : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Wait 500us for the oscillator to be back up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int pca9685_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct pca9685 *pca = to_pca(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long long duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (period_ns != pca->period_ns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) prescale = DIV_ROUND_CLOSEST(PCA9685_OSC_CLOCK_MHZ * period_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PCA9685_COUNTER_RANGE * 1000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (prescale >= PCA9685_PRESCALE_MIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) prescale <= PCA9685_PRESCALE_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Putting the chip briefly into SLEEP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * at this point won't interfere with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * pm_runtime framework, because the pm_runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * state is guaranteed active here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Put chip into sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pca9685_set_sleep_mode(pca, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Change the chip-wide output frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) regmap_write(pca->regmap, PCA9685_PRESCALE, prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Wake the chip up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pca9685_set_sleep_mode(pca, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pca->period_ns = period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "prescaler not set: period out of bounds!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (duty_ns < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) reg = PCA9685_ALL_LED_OFF_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) reg = LED_N_OFF_H(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) regmap_write(pca->regmap, reg, LED_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (duty_ns == period_ns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Clear both OFF registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) reg = PCA9685_ALL_LED_OFF_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) reg = LED_N_OFF_L(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) regmap_write(pca->regmap, reg, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reg = PCA9685_ALL_LED_OFF_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) reg = LED_N_OFF_H(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_write(pca->regmap, reg, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Set the full ON bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) reg = PCA9685_ALL_LED_ON_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reg = LED_N_ON_H(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) regmap_write(pca->regmap, reg, LED_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) duty = PCA9685_COUNTER_RANGE * (unsigned long long)duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) duty = DIV_ROUND_UP_ULL(duty, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reg = PCA9685_ALL_LED_OFF_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reg = LED_N_OFF_L(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_write(pca->regmap, reg, (int)duty & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) reg = PCA9685_ALL_LED_OFF_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) reg = LED_N_OFF_H(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regmap_write(pca->regmap, reg, ((int)duty >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Clear the full ON bit, otherwise the set OFF time has no effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) reg = PCA9685_ALL_LED_ON_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) reg = LED_N_ON_H(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) regmap_write(pca->regmap, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int pca9685_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct pca9685 *pca = to_pca(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * The PWM subsystem does not support a pre-delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * So, set the ON-timeout to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) reg = PCA9685_ALL_LED_ON_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reg = LED_N_ON_L(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) regmap_write(pca->regmap, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reg = PCA9685_ALL_LED_ON_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) reg = LED_N_ON_H(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) regmap_write(pca->regmap, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Clear the full-off bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * It has precedence over the others and must be off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) reg = PCA9685_ALL_LED_OFF_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) reg = LED_N_OFF_H(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) regmap_update_bits(pca->regmap, reg, LED_FULL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void pca9685_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct pca9685 *pca = to_pca(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) reg = PCA9685_ALL_LED_OFF_H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) reg = LED_N_OFF_H(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) regmap_write(pca->regmap, reg, LED_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Clear the LED_OFF counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (pwm->hwpwm >= PCA9685_MAXCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) reg = PCA9685_ALL_LED_OFF_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) reg = LED_N_OFF_L(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) regmap_write(pca->regmap, reg, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int pca9685_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct pca9685 *pca = to_pca(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (pca9685_pwm_test_and_set_inuse(pca, pwm->hwpwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pm_runtime_get_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void pca9685_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct pca9685 *pca = to_pca(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pca9685_pwm_disable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pm_runtime_put(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pca9685_pwm_clear_inuse(pca, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct pwm_ops pca9685_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .enable = pca9685_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .disable = pca9685_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .config = pca9685_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .request = pca9685_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .free = pca9685_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const struct regmap_config pca9685_regmap_i2c_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .max_register = PCA9685_NUMREGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int pca9685_pwm_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct pca9685 *pca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pca = devm_kzalloc(&client->dev, sizeof(*pca), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!pca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pca->regmap = devm_regmap_init_i2c(client, &pca9685_regmap_i2c_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (IS_ERR(pca->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = PTR_ERR(pca->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(&client->dev, "Failed to initialize register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pca->period_ns = PCA9685_DEFAULT_PERIOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) i2c_set_clientdata(client, pca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) regmap_read(pca->regmap, PCA9685_MODE2, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (device_property_read_bool(&client->dev, "invert"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) reg |= MODE2_INVRT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) reg &= ~MODE2_INVRT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (device_property_read_bool(&client->dev, "open-drain"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) reg &= ~MODE2_OUTDRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) reg |= MODE2_OUTDRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) regmap_write(pca->regmap, PCA9685_MODE2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Disable all LED ALLCALL and SUBx addresses to avoid bus collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) regmap_read(pca->regmap, PCA9685_MODE1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) reg &= ~(MODE1_ALLCALL | MODE1_SUB1 | MODE1_SUB2 | MODE1_SUB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) regmap_write(pca->regmap, PCA9685_MODE1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Clear all "full off" bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) regmap_write(pca->regmap, PCA9685_ALL_LED_OFF_L, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) regmap_write(pca->regmap, PCA9685_ALL_LED_OFF_H, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pca->chip.ops = &pca9685_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Add an extra channel for ALL_LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pca->chip.npwm = PCA9685_MAXCHAN + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pca->chip.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pca->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = pwmchip_add(&pca->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = pca9685_pwm_gpio_probe(pca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pwmchip_remove(&pca->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* The chip comes out of power-up in the active state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Enable will put the chip into suspend, which is what we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * want as all outputs are disabled at this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int pca9685_pwm_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct pca9685 *pca = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = pwmchip_remove(&pca->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int __maybe_unused pca9685_pwm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct pca9685 *pca = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pca9685_set_sleep_mode(pca, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int __maybe_unused pca9685_pwm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct pca9685 *pca = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pca9685_set_sleep_mode(pca, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const struct i2c_device_id pca9685_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { "pca9685", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_DEVICE_TABLE(i2c, pca9685_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct acpi_device_id pca9685_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { "INT3492", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MODULE_DEVICE_TABLE(acpi, pca9685_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct of_device_id pca9685_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { .compatible = "nxp,pca9685-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_DEVICE_TABLE(of, pca9685_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const struct dev_pm_ops pca9685_pwm_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) SET_RUNTIME_PM_OPS(pca9685_pwm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pca9685_pwm_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct i2c_driver pca9685_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .name = "pca9685-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .acpi_match_table = ACPI_PTR(pca9685_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .of_match_table = of_match_ptr(pca9685_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .pm = &pca9685_pwm_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .probe = pca9685_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .remove = pca9685_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .id_table = pca9685_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) module_i2c_driver(pca9685_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MODULE_DESCRIPTION("PWM driver for PCA9685");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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