^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/stmp_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TOG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PWM_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PWM_ACTIVE0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PWM_PERIOD0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PERIOD_PERIOD(p) ((p) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PERIOD_PERIOD_MAX 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PERIOD_ACTIVE_HIGH (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PERIOD_ACTIVE_LOW (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PERIOD_INACTIVE_HIGH (3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PERIOD_INACTIVE_LOW (2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PERIOD_CDIV(div) (((div) & 0x7) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PERIOD_CDIV_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const u8 cdiv_shift[PERIOD_CDIV_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0, 1, 2, 3, 4, 6, 8, 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct mxs_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int ret, div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int period_cycles, duty_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int pol_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * If the PWM channel is disabled, make sure to turn on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * clock before calling clk_get_rate() and writing to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * registers. Otherwise, just keep it enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (!pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = clk_prepare_enable(mxs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (!state->enabled && pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) rate = clk_get_rate(mxs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) c = rate >> cdiv_shift[div];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) c = c * state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) do_div(c, 1000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (c < PERIOD_PERIOD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (div >= PERIOD_CDIV_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) period_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) c *= state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) do_div(c, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) duty_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * The data sheet the says registers must be written to in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * this order (ACTIVEn, then PERIODn). Also, the new settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * only take effect at the beginning of a new period, avoiding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * glitches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pol_bits = state->polarity == PWM_POLARITY_NORMAL ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel(duty_cycles << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * The clock was enabled above. Just enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * the channel in the control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clk_disable_unprepare(mxs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct pwm_ops mxs_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .apply = mxs_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int mxs_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct mxs_pwm_chip *mxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!mxs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mxs->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (IS_ERR(mxs->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return PTR_ERR(mxs->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mxs->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (IS_ERR(mxs->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return PTR_ERR(mxs->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mxs->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mxs->chip.ops = &mxs_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mxs->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mxs->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mxs->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* FIXME: Only do this if the PWM isn't already running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = stmp_reset_block(mxs->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = pwmchip_add(&mxs->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) platform_set_drvdata(pdev, mxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int mxs_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return pwmchip_remove(&mxs->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct of_device_id mxs_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .compatible = "fsl,imx23-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct platform_driver mxs_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "mxs-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .of_match_table = mxs_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .probe = mxs_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .remove = mxs_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) module_platform_driver(mxs_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_ALIAS("platform:mxs-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_DESCRIPTION("Freescale MXS PWM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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