^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MediaTek display pulse-width-modulation controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: YH Huang <yh.huang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DISP_PWM_EN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PWM_CLKDIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PWM_CLKDIV_MAX 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWM_PERIOD_BIT_WIDTH 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWM_HIGH_WIDTH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mtk_pwm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int con0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 con0_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int con1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool has_commit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int commit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int commit_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int bls_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 bls_debug_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct mtk_disp_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct mtk_pwm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk *clk_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk *clk_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return container_of(chip, struct mtk_disp_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *address = mdp->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) value = readl(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) value |= data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel(value, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 clk_div, period, high_width, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u64 div, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Find period, high_width and clk_div to suit duty_ns and period_ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Calculate proper div value to keep period value in the bound.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rate = clk_get_rate(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PWM_PERIOD_BIT_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (clk_div > PWM_CLKDIV_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) div = NSEC_PER_SEC * (clk_div + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) period = div64_u64(rate * period_ns, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (period > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) period--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) high_width = div64_u64(rate * duty_ns, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) err = clk_enable(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) err = clk_enable(mdp->clk_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_disable(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PWM_CLKDIV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk_div << PWM_CLKDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (mdp->data->has_commit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mdp->data->commit_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mdp->data->commit_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mdp->data->commit_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_disable(mdp->clk_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk_disable(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) err = clk_enable(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = clk_enable(mdp->clk_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clk_disable(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mdp->data->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk_disable(mdp->clk_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clk_disable(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct pwm_ops mtk_disp_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .config = mtk_disp_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .enable = mtk_disp_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .disable = mtk_disp_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int mtk_disp_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct mtk_disp_pwm *mdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!mdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mdp->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mdp->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (IS_ERR(mdp->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return PTR_ERR(mdp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mdp->clk_main = devm_clk_get(&pdev->dev, "main");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(mdp->clk_main))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return PTR_ERR(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (IS_ERR(mdp->clk_mm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return PTR_ERR(mdp->clk_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = clk_prepare(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = clk_prepare(mdp->clk_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto disable_clk_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mdp->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mdp->chip.ops = &mtk_disp_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mdp->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mdp->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = pwmchip_add(&mdp->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto disable_clk_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) platform_set_drvdata(pdev, mdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * For MT2701, disable double buffer before writing register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!mdp->data->has_commit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mdp->data->bls_debug_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mdp->data->bls_debug_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mdp->data->con0_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mdp->data->con0_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) disable_clk_mm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) clk_unprepare(mdp->clk_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) disable_clk_main:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_unprepare(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int mtk_disp_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = pwmchip_remove(&mdp->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk_unprepare(mdp->clk_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clk_unprepare(mdp->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct mtk_pwm_data mt2701_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .enable_mask = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .con0 = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .con0_sel = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .con1 = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .has_commit = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .bls_debug = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .bls_debug_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct mtk_pwm_data mt8173_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .con0 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .con0_sel = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .con1 = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .has_commit = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .commit = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .commit_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct mtk_pwm_data mt8183_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .enable_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .con0 = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .con0_sel = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .con1 = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .has_commit = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .bls_debug = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .bls_debug_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct of_device_id mtk_disp_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct platform_driver mtk_disp_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .name = "mediatek-disp-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .of_match_table = mtk_disp_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .probe = mtk_disp_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .remove = mtk_disp_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) module_platform_driver(mtk_disp_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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