^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PWM controller driver for Amlogic Meson SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This PWM is only a set of Gates, Dividers and Counters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * PWM output is achieved by calculating a clock that permits calculating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * two periods (low and high). The counter then has to be set to switch after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * N cycles for the first half period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The hardware has no "polarity" setting. This driver reverses the period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * cycles (the low length is inverted with the high length) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * from the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Setting the duty cycle will disable and re-enable the PWM output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Disabling the PWM stops the output immediately (without waiting for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * current period to complete first).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The public S912 (GXM) datasheet contains some documentation for this PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * controller starting on page 543:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * An updated version of this IP block is found in S922X (G12B) SoCs. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * datasheet contains the description for this IP block revision starting at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * page 1084:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Copyright (C) 2014 Amlogic, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_PWM_A 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_PWM_B 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PWM_LOW_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PWM_HIGH_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_MISC_AB 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MISC_B_CLK_EN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MISC_A_CLK_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MISC_CLK_DIV_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MISC_B_CLK_DIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MISC_A_CLK_DIV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MISC_B_CLK_SEL_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MISC_A_CLK_SEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MISC_CLK_SEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MISC_B_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MISC_A_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MESON_NUM_PWMS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct meson_pwm_channel_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 clk_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 clk_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 clk_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 pwm_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .reg_offset = REG_PWM_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .clk_en_mask = MISC_A_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .pwm_en_mask = MISC_A_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .reg_offset = REG_PWM_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .clk_en_mask = MISC_B_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .pwm_en_mask = MISC_B_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct meson_pwm_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct meson_pwm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct meson_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const struct meson_pwm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct meson_pwm_channel channels[MESON_NUM_PWMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Protects register (write) access to the REG_MISC_AB register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * that is shared between the two PWMs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return container_of(chip, struct meson_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct meson_pwm *meson = to_meson_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct meson_pwm_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct device *dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) channel = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) channel = &meson->channels[pwm->hwpwm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (channel->clk_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err = clk_set_parent(channel->clk, channel->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_err(dev, "failed to set parent %s for %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __clk_get_name(channel->clk_parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __clk_get_name(channel->clk), err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) err = clk_prepare_enable(channel->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(dev, "failed to enable clock %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __clk_get_name(channel->clk), err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return pwm_set_chip_data(pwm, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk_disable_unprepare(channel->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int duty, period, pre_div, cnt, duty_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long fin_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) duty = state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) period = state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (state->polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) duty = period - duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) fin_freq = clk_get_rate(channel->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (fin_freq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(meson->chip.dev, "invalid source clock frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (pre_div > MISC_CLK_DIV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(meson->chip.dev, "unable to get period pre_div\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (cnt > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(meson->chip.dev, "unable to get period cnt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pre_div, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (duty == period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) channel->pre_div = pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) channel->hi = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) channel->lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else if (duty == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) channel->pre_div = pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) channel->hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) channel->lo = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Then check is we can have the duty with the same pre_div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) duty_cnt = div64_u64(fin_freq * (u64)duty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) NSEC_PER_SEC * (pre_div + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (duty_cnt > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(meson->chip.dev, "unable to get duty cycle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) duty, pre_div, duty_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) channel->pre_div = pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) channel->hi = duty_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) channel->lo = cnt - duty_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct meson_pwm_channel_data *channel_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_lock_irqsave(&meson->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) value = readl(meson->base + REG_MISC_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) value |= channel->pre_div << channel_data->clk_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) value |= channel_data->clk_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(value, meson->base + REG_MISC_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FIELD_PREP(PWM_LOW_MASK, channel->lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(value, meson->base + channel_data->reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) value = readl(meson->base + REG_MISC_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) value |= channel_data->pwm_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(value, meson->base + REG_MISC_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_unlock_irqrestore(&meson->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) spin_lock_irqsave(&meson->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) value = readl(meson->base + REG_MISC_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writel(value, meson->base + REG_MISC_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irqrestore(&meson->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct meson_pwm *meson = to_meson_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (state->polarity == PWM_POLARITY_INVERSED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * This IP block revision doesn't have an "always high"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * setting which we can use for "inverted disabled".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Instead we achieve this using the same settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * that we use a pre_div of 0 (to get the shortest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * possible duration for one "count") and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * "period == duty_cycle". This results in a signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * which is LOW for one "count", while being HIGH for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * the rest of the (so the signal is HIGH for slightly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * less than 100% of the period, but this is the best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * we can achieve).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) channel->pre_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) channel->hi = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) channel->lo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) meson_pwm_enable(meson, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) meson_pwm_disable(meson, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) err = meson_pwm_calc(meson, pwm, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) meson_pwm_enable(meson, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct pwm_device *pwm, u32 cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct meson_pwm *meson = to_meson_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct meson_pwm_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long fin_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 fin_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* to_meson_pwm() can only be used after .get_state() is called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) channel = &meson->channels[pwm->hwpwm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) fin_freq = clk_get_rate(channel->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (fin_freq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return cnt * fin_ns * (channel->pre_div + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct meson_pwm *meson = to_meson_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct meson_pwm_channel_data *channel_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct meson_pwm_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 value, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) channel = &meson->channels[pwm->hwpwm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) value = readl(meson->base + REG_MISC_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) state->enabled = (value & tmp) == tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) tmp = value >> channel_data->clk_div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) value = readl(meson->base + channel_data->reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) channel->lo = FIELD_GET(PWM_LOW_MASK, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (channel->lo == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) state->duty_cycle = state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } else if (channel->lo >= channel->hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) state->period = meson_pwm_cnt_to_ns(chip, pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) channel->lo + channel->hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) channel->hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) state->period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) state->duty_cycle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct pwm_ops meson_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .request = meson_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .free = meson_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .apply = meson_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .get_state = meson_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char * const pwm_meson8b_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "xtal", "vid_pll", "fclk_div4", "fclk_div3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct meson_pwm_data pwm_meson8b_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .parent_names = pwm_meson8b_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const char * const pwm_gxbb_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct meson_pwm_data pwm_gxbb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .parent_names = pwm_gxbb_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Only the 2 first inputs of the GXBB AO PWMs are valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * The last 2 are grounded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const char * const pwm_gxbb_ao_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "xtal", "clk81"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct meson_pwm_data pwm_gxbb_ao_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .parent_names = pwm_gxbb_ao_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const char * const pwm_axg_ee_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct meson_pwm_data pwm_axg_ee_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .parent_names = pwm_axg_ee_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const char * const pwm_axg_ao_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "aoclk81", "xtal", "fclk_div4", "fclk_div5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct meson_pwm_data pwm_axg_ao_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .parent_names = pwm_axg_ao_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const char * const pwm_g12a_ao_ab_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "xtal", "aoclk81", "fclk_div4", "fclk_div5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .parent_names = pwm_g12a_ao_ab_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const char * const pwm_g12a_ao_cd_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "xtal", "aoclk81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .parent_names = pwm_g12a_ao_cd_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const char * const pwm_g12a_ee_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const struct meson_pwm_data pwm_g12a_ee_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .parent_names = pwm_g12a_ee_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct of_device_id meson_pwm_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .compatible = "amlogic,meson8b-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .data = &pwm_meson8b_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .compatible = "amlogic,meson-gxbb-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .data = &pwm_gxbb_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .compatible = "amlogic,meson-gxbb-ao-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .data = &pwm_gxbb_ao_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .compatible = "amlogic,meson-axg-ee-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .data = &pwm_axg_ee_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .compatible = "amlogic,meson-axg-ao-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .data = &pwm_axg_ao_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .compatible = "amlogic,meson-g12a-ee-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .data = &pwm_g12a_ee_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .compatible = "amlogic,meson-g12a-ao-pwm-ab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .data = &pwm_g12a_ao_ab_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .compatible = "amlogic,meson-g12a-ao-pwm-cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .data = &pwm_g12a_ao_cd_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MODULE_DEVICE_TABLE(of, meson_pwm_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int meson_pwm_init_channels(struct meson_pwm *meson)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct device *dev = meson->chip.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) char name[255];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) for (i = 0; i < meson->chip.npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct meson_pwm_channel *channel = &meson->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) init.ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) init.parent_names = meson->data->parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) init.num_parents = meson->data->num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) channel->mux.reg = meson->base + REG_MISC_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) channel->mux.shift =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) meson_pwm_per_channel_data[i].clk_sel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) channel->mux.mask = MISC_CLK_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) channel->mux.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) channel->mux.lock = &meson->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) channel->mux.table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) channel->mux.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) channel->clk = devm_clk_register(dev, &channel->mux.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (IS_ERR(channel->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err = PTR_ERR(channel->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(dev, "failed to register %s: %d\n", name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) snprintf(name, sizeof(name), "clkin%u", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) channel->clk_parent = devm_clk_get_optional(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (IS_ERR(channel->clk_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return PTR_ERR(channel->clk_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int meson_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct meson_pwm *meson;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!meson)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) meson->base = devm_ioremap_resource(&pdev->dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (IS_ERR(meson->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return PTR_ERR(meson->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spin_lock_init(&meson->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) meson->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) meson->chip.ops = &meson_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) meson->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) meson->chip.npwm = MESON_NUM_PWMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) meson->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) meson->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) meson->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) err = meson_pwm_init_channels(meson);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err = pwmchip_add(&meson->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) platform_set_drvdata(pdev, meson);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int meson_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct meson_pwm *meson = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return pwmchip_remove(&meson->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct platform_driver meson_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "meson-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .of_match_table = meson_pwm_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .probe = meson_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .remove = meson_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) module_platform_driver(meson_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MODULE_LICENSE("Dual BSD/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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