^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MediaTek Pulse Width Modulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* PWM registers and bits definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWMCON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWMHDUR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PWMLDUR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWMGDUR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PWMWAVENUM 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PWMDWIDTH 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PWM45DWIDTH_FIXUP 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PWMTHRES 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PWM45THRES_FIXUP 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PWM_CLK_DIV_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pwm_mediatek_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int num_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bool pwm45_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * struct pwm_mediatek_chip - struct representing PWM chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @chip: linux PWM chip representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @regs: base address of PWM chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @clk_top: the top clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @clk_main: the clock used by PWM core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @clk_pwms: the clock used by each PWM channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @clk_freq: the fix clock frequency of legacy MIPS SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @soc: pointer to chip's platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct pwm_mediatek_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *clk_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *clk_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk **clk_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct pwm_mediatek_of_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const unsigned int pwm_mediatek_reg_offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline struct pwm_mediatek_chip *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) to_pwm_mediatek_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return container_of(chip, struct pwm_mediatek_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = clk_prepare_enable(pc->clk_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ret = clk_prepare_enable(pc->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) goto disable_clk_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) goto disable_clk_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) disable_clk_main:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clk_disable_unprepare(pc->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) disable_clk_top:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clk_disable_unprepare(pc->clk_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk_disable_unprepare(pc->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk_disable_unprepare(pc->clk_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int num, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int num, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg_thres = PWMTHRES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u64 resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = pwm_mediatek_clk_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Using resolution in picosecond gets accuracy higher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) resolution = (u64)NSEC_PER_SEC * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) while (cnt_period > 8191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) resolution *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clkdiv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (clkdiv > PWM_CLK_DIV_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pwm_mediatek_clk_disable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(chip->dev, "period %d not supported\n", period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * from the other PWMs on MT7623.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) reg_width = PWM45DWIDTH_FIXUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) reg_thres = PWM45THRES_FIXUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pwm_mediatek_clk_disable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = pwm_mediatek_clk_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) value = readl(pc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) value |= BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writel(value, pc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) value = readl(pc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) value &= ~BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(value, pc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pwm_mediatek_clk_disable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct pwm_ops pwm_mediatek_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .config = pwm_mediatek_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .enable = pwm_mediatek_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .disable = pwm_mediatek_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int pwm_mediatek_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct pwm_mediatek_chip *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pc->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pc->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (IS_ERR(pc->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return PTR_ERR(pc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sizeof(*pc->clk_pwms), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!pc->clk_pwms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pc->clk_top = devm_clk_get(&pdev->dev, "top");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (IS_ERR(pc->clk_top)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(&pdev->dev, "clock: top fail: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PTR_ERR(pc->clk_top));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return PTR_ERR(pc->clk_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pc->clk_main = devm_clk_get(&pdev->dev, "main");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (IS_ERR(pc->clk_main)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(&pdev->dev, "clock: main fail: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PTR_ERR(pc->clk_main));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return PTR_ERR(pc->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) for (i = 0; i < pc->soc->num_pwms; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) snprintf(name, sizeof(name), "pwm%d", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (IS_ERR(pc->clk_pwms[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(&pdev->dev, "clock: %s fail: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) name, PTR_ERR(pc->clk_pwms[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return PTR_ERR(pc->clk_pwms[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pc->chip.ops = &pwm_mediatek_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pc->chip.npwm = pc->soc->num_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = pwmchip_add(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int pwm_mediatek_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct pwm_mediatek_of_data mt2712_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .num_pwms = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .pwm45_fixup = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct pwm_mediatek_of_data mt7622_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .num_pwms = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .pwm45_fixup = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct pwm_mediatek_of_data mt7623_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .num_pwms = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .pwm45_fixup = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct pwm_mediatek_of_data mt7628_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .num_pwms = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .pwm45_fixup = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct pwm_mediatek_of_data mt7629_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .num_pwms = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .pwm45_fixup = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct pwm_mediatek_of_data mt8516_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .num_pwms = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .pwm45_fixup = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct of_device_id pwm_mediatek_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct platform_driver pwm_mediatek_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "pwm-mediatek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .of_match_table = pwm_mediatek_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .probe = pwm_mediatek_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .remove = pwm_mediatek_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) module_platform_driver(pwm_mediatek_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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