^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Low Power Subsystem PWM controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Chew Kean Ho <kean.ho.chew@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Alan Cox <alan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pwm-lpss.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PWM 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWM_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWM_SW_UPDATE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PWM_BASE_UNIT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWM_ON_TIME_DIV_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Size of each PWM register space if multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PWM_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return container_of(chip, struct pwm_lpss_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const unsigned int ms = 500 * USEC_PER_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * PWM Configuration register has SW_UPDATE bit that is set when a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * configuration is written to the register. The bit is automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * cleared at the start of the next output cycle by the IP block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * If one writes a new configuration to the register while it still has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * the bit enabled, PWM may freeze. That is, while one can still write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * to the register, it won't have an effect. Thus, we try to sleep long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * enough that the bit gets cleared and make sure the bit is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * enabled while we update the configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long long on_time_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long c = lpwm->info->clk_rate, base_unit_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long long base_unit, freq = NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) do_div(freq, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * The equation is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * base_unit = round(base_unit_range * freq / c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) base_unit_range = BIT(lpwm->info->base_unit_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) freq *= base_unit_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* base_unit must not be 0 and we also want to avoid overflowing it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) base_unit = clamp_val(base_unit, 1, base_unit_range - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) on_time_div = 255ULL * duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) do_div(on_time_div, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) on_time_div = 255ULL - on_time_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ctrl = pwm_lpss_read(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ctrl &= ~PWM_ON_TIME_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ctrl |= on_time_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pwm_lpss_write(pwm, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = pwm_lpss_is_updating(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = pwm_lpss_wait_for_update(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct pwm_lpss_chip *lpwm = to_lpwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pm_runtime_get_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pm_runtime_put(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else if (pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pm_runtime_put(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct pwm_lpss_chip *lpwm = to_lpwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long base_unit_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long long base_unit, freq, on_time_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pm_runtime_get_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) base_unit_range = BIT(lpwm->info->base_unit_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ctrl = pwm_lpss_read(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) freq = base_unit * lpwm->info->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) do_div(freq, base_unit_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (freq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) state->period = NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) state->period = NSEC_PER_SEC / (unsigned long)freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) on_time_div *= state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) do_div(on_time_div, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) state->duty_cycle = on_time_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) state->enabled = !!(ctrl & PWM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pm_runtime_put(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct pwm_ops pwm_lpss_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .apply = pwm_lpss_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .get_state = pwm_lpss_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const struct pwm_lpss_boardinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct pwm_lpss_chip *lpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (WARN_ON(info->npwm > MAX_PWMS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!lpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) lpwm->regs = devm_ioremap_resource(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (IS_ERR(lpwm->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ERR_CAST(lpwm->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) lpwm->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) c = lpwm->info->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) lpwm->chip.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) lpwm->chip.ops = &pwm_lpss_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) lpwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) lpwm->chip.npwm = info->npwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = pwmchip_add(&lpwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(dev, "failed to add PWM chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for (i = 0; i < lpwm->info->npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ctrl & PWM_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pm_runtime_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return lpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) EXPORT_SYMBOL_GPL(pwm_lpss_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) for (i = 0; i < lpwm->info->npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (pwm_is_enabled(&lpwm->chip.pwms[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pm_runtime_put(lpwm->chip.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return pwmchip_remove(&lpwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EXPORT_SYMBOL_GPL(pwm_lpss_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_DESCRIPTION("PWM driver for Intel LPSS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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