^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Low Power Subsystem PWM controller PCI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Derived from the original pwm-lpss.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pwm-lpss.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* BayTrail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .clk_rate = 25000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .npwm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .base_unit_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Braswell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .clk_rate = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .npwm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .base_unit_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Broxton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .clk_rate = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .npwm = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .base_unit_bits = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .bypass = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Tangier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct pwm_lpss_boardinfo pwm_lpss_tng_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .clk_rate = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .npwm = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .base_unit_bits = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int pwm_lpss_probe_pci(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const struct pwm_lpss_boardinfo *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pwm_lpss_chip *lpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) err = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) info = (struct pwm_lpss_boardinfo *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) lpwm = pwm_lpss_probe(&pdev->dev, &pdev->resource[0], info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (IS_ERR(lpwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return PTR_ERR(lpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pci_set_drvdata(pdev, lpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pm_runtime_allow(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void pwm_lpss_remove_pci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct pwm_lpss_chip *lpwm = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pm_runtime_forbid(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pwm_lpss_remove(lpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int pwm_lpss_runtime_suspend_pci(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * The PCI core will handle transition to D3 automatically. We only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * need to provide runtime PM hooks for that to happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int pwm_lpss_runtime_resume_pci(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct dev_pm_ops pwm_lpss_pci_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SET_RUNTIME_PM_OPS(pwm_lpss_runtime_suspend_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pwm_lpss_runtime_resume_pci, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct pci_device_id pwm_lpss_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { PCI_VDEVICE(INTEL, 0x0ac8), (unsigned long)&pwm_lpss_bxt_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { PCI_VDEVICE(INTEL, 0x0f08), (unsigned long)&pwm_lpss_byt_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { PCI_VDEVICE(INTEL, 0x0f09), (unsigned long)&pwm_lpss_byt_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { PCI_VDEVICE(INTEL, 0x11a5), (unsigned long)&pwm_lpss_tng_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)&pwm_lpss_bxt_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { PCI_VDEVICE(INTEL, 0x2288), (unsigned long)&pwm_lpss_bsw_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { PCI_VDEVICE(INTEL, 0x2289), (unsigned long)&pwm_lpss_bsw_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { PCI_VDEVICE(INTEL, 0x31c8), (unsigned long)&pwm_lpss_bxt_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { PCI_VDEVICE(INTEL, 0x5ac8), (unsigned long)&pwm_lpss_bxt_info},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct pci_driver pwm_lpss_driver_pci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .name = "pwm-lpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .id_table = pwm_lpss_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .probe = pwm_lpss_probe_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .remove = pwm_lpss_remove_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .pm = &pwm_lpss_pci_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) module_pci_driver(pwm_lpss_driver_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODULE_DESCRIPTION("PWM PCI driver for Intel LPSS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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