^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct lpc32xx_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PWM_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWM_PIN_LEVEL BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define to_lpc32xx_pwm_chip(_chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) container_of(_chip, struct lpc32xx_pwm_chip, chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int period_cycles, duty_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) c = clk_get_rate(lpc32xx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* The highest acceptable divisor is 256, which is represented by 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) period_cycles = div64_u64(c * period_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (unsigned long long)NSEC_PER_SEC * 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (!period_cycles || period_cycles > 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (period_cycles == 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) period_cycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Compute 256 x #duty/period value and care for corner cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (!duty_cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) duty_cycles = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (duty_cycles > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) duty_cycles = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val = readl(lpc32xx->base + (pwm->hwpwm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val &= ~0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) val |= (period_cycles << 8) | duty_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel(val, lpc32xx->base + (pwm->hwpwm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = clk_prepare_enable(lpc32xx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val = readl(lpc32xx->base + (pwm->hwpwm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val |= PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel(val, lpc32xx->base + (pwm->hwpwm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) val = readl(lpc32xx->base + (pwm->hwpwm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val &= ~PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel(val, lpc32xx->base + (pwm->hwpwm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_disable_unprepare(lpc32xx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct pwm_ops lpc32xx_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .config = lpc32xx_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .enable = lpc32xx_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .disable = lpc32xx_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int lpc32xx_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct lpc32xx_pwm_chip *lpc32xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!lpc32xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (IS_ERR(lpc32xx->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return PTR_ERR(lpc32xx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (IS_ERR(lpc32xx->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return PTR_ERR(lpc32xx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) lpc32xx->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) lpc32xx->chip.ops = &lpc32xx_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) lpc32xx->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) lpc32xx->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* If PWM is disabled, configure the output to the default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val &= ~PWM_PIN_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = pwmchip_add(&lpc32xx->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) platform_set_drvdata(pdev, lpc32xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int lpc32xx_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) for (i = 0; i < lpc32xx->chip.npwm; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pwm_disable(&lpc32xx->chip.pwms[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return pwmchip_remove(&lpc32xx->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .compatible = "nxp,lpc3220-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct platform_driver lpc32xx_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "lpc32xx-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .of_match_table = lpc32xx_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .probe = lpc32xx_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .remove = lpc32xx_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) module_platform_driver(lpc32xx_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_ALIAS("platform:lpc32xx-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MODULE_DESCRIPTION("LPC32XX PWM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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