^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI/National Semiconductor LP3943 PWM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Milo Kim <milo.kim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/lp3943.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LP3943_MAX_DUTY 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LP3943_MIN_PERIOD 6250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LP3943_MAX_PERIOD 1600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct lp3943_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct lp3943 *lp3943;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct lp3943_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline struct lp3943_pwm *to_lp3943_pwm(struct pwm_chip *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return container_of(_chip, struct lp3943_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct lp3943_pwm_map *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) lp3943_pwm_request_map(struct lp3943_pwm *lp3943_pwm, int hwpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct lp3943_platform_data *pdata = lp3943_pwm->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct lp3943 *lp3943 = lp3943_pwm->lp3943;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct lp3943_pwm_map *pwm_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int i, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pwm_map = kzalloc(sizeof(*pwm_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (!pwm_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) pwm_map->output = pdata->pwms[hwpwm]->output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) for (i = 0; i < pwm_map->num_outputs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) offset = pwm_map->output[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Return an error if the pin is already assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (test_and_set_bit(offset, &lp3943->pin_used)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) kfree(pwm_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return pwm_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int lp3943_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct lp3943_pwm_map *pwm_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pwm_map = lp3943_pwm_request_map(lp3943_pwm, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (IS_ERR(pwm_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return PTR_ERR(pwm_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return pwm_set_chip_data(pwm, pwm_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void lp3943_pwm_free_map(struct lp3943_pwm *lp3943_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct lp3943_pwm_map *pwm_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct lp3943 *lp3943 = lp3943_pwm->lp3943;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int i, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) for (i = 0; i < pwm_map->num_outputs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) offset = pwm_map->output[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clear_bit(offset, &lp3943->pin_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) kfree(pwm_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void lp3943_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct lp3943_pwm_map *pwm_map = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) lp3943_pwm_free_map(lp3943_pwm, pwm_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int lp3943_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct lp3943 *lp3943 = lp3943_pwm->lp3943;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 val, reg_duty, reg_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * How to configure the LP3943 PWMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * 1) Period = 6250 ~ 1600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 2) Prescale = period / 6250 -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * 3) Duty = input duty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Prescale and duty are register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (pwm->hwpwm == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg_prescale = LP3943_REG_PRESCALE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg_duty = LP3943_REG_PWM0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg_prescale = LP3943_REG_PRESCALE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg_duty = LP3943_REG_PWM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) period_ns = clamp(period_ns, LP3943_MIN_PERIOD, LP3943_MAX_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) val = (u8)(period_ns / LP3943_MIN_PERIOD - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err = lp3943_write_byte(lp3943, reg_prescale, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val = (u8)(duty_ns * LP3943_MAX_DUTY / period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return lp3943_write_byte(lp3943, reg_duty, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int lp3943_pwm_set_mode(struct lp3943_pwm *lp3943_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct lp3943_pwm_map *pwm_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct lp3943 *lp3943 = lp3943_pwm->lp3943;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const struct lp3943_reg_cfg *mux = lp3943->mux_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int i, index, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) for (i = 0; i < pwm_map->num_outputs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) index = pwm_map->output[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) err = lp3943_update_bits(lp3943, mux[index].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mux[index].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val << mux[index].shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int lp3943_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct lp3943_pwm_map *pwm_map = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (pwm->hwpwm == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val = LP3943_DIM_PWM0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val = LP3943_DIM_PWM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Each PWM generator is set to control any of outputs of LP3943.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * To enable/disable the PWM, these output pins should be configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return lp3943_pwm_set_mode(lp3943_pwm, pwm_map, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void lp3943_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct lp3943_pwm *lp3943_pwm = to_lp3943_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct lp3943_pwm_map *pwm_map = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * LP3943 outputs are open-drain, so the pin should be configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * when the PWM is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) lp3943_pwm_set_mode(lp3943_pwm, pwm_map, LP3943_GPIO_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct pwm_ops lp3943_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .request = lp3943_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .free = lp3943_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .config = lp3943_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .enable = lp3943_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .disable = lp3943_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int lp3943_pwm_parse_dt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct lp3943_pwm *lp3943_pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const char * const name[] = { "ti,pwm0", "ti,pwm1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct lp3943_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct lp3943_pwm_map *pwm_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum lp3943_pwm_output *output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int i, err, proplen, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 num_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Read the output map configuration from the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Each of the two PWM generators can drive zero or more outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) for (i = 0; i < LP3943_NUM_PWMS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!of_get_property(node, name[i], &proplen))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) num_outputs = proplen / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (num_outputs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) output = devm_kcalloc(dev, num_outputs, sizeof(*output),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) err = of_property_read_u32_array(node, name[i], output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) num_outputs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pwm_map = devm_kzalloc(dev, sizeof(*pwm_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!pwm_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pwm_map->output = output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pwm_map->num_outputs = num_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pdata->pwms[i] = pwm_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) lp3943_pwm->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int lp3943_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct lp3943 *lp3943 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct lp3943_pwm *lp3943_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) lp3943_pwm = devm_kzalloc(&pdev->dev, sizeof(*lp3943_pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!lp3943_pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) lp3943_pwm->pdata = lp3943->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!lp3943_pwm->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (IS_ENABLED(CONFIG_OF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = lp3943_pwm_parse_dt(&pdev->dev, lp3943_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) lp3943_pwm->lp3943 = lp3943;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) lp3943_pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) lp3943_pwm->chip.ops = &lp3943_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) lp3943_pwm->chip.npwm = LP3943_NUM_PWMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) lp3943_pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) platform_set_drvdata(pdev, lp3943_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return pwmchip_add(&lp3943_pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int lp3943_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct lp3943_pwm *lp3943_pwm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return pwmchip_remove(&lp3943_pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct of_device_id lp3943_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { .compatible = "ti,lp3943-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_DEVICE_TABLE(of, lp3943_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct platform_driver lp3943_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .probe = lp3943_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .remove = lp3943_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "lp3943-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .of_match_table = of_match_ptr(lp3943_pwm_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) module_platform_driver(lp3943_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MODULE_DESCRIPTION("LP3943 PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MODULE_ALIAS("platform:lp3943-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_AUTHOR("Milo Kim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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