^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * JZ4740 platform PWM support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - The .apply callback doesn't complete the currently running period before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * reconfiguring the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/ingenic-tcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int num_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct jz4740_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return container_of(chip, struct jz4740_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Enable all TCU channels for PWM use by default except channels 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) device_property_read_u32(jz->chip.dev->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "ingenic,pwm-channels-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) &pwm_channels_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return !!(pwm_channels_mask & BIT(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct jz4740_pwm_chip *jz = to_jz4740(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clk = clk_get(chip->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return dev_err_probe(chip->dev, PTR_ERR(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) err = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pwm_set_chip_data(pwm, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk *clk = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct jz4740_pwm_chip *jz = to_jz4740(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Enable PWM output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Start counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct jz4740_pwm_chip *jz = to_jz4740(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Set duty > period. This trick allows the TCU channels in TCU2 mode to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * properly return to their init level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Disable PWM output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * counter is stopped, while in TCU1 mode the order does not matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) TCU_TCSR_PWM_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Stop counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk *clk = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long period, duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Limit the clock to a maximum rate that still gives us a period value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * which fits in 16 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) do_div(tmp, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * /!\ IMPORTANT NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * This code relies on the fact that clk_round_rate() will always round
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * down, which is not a valid assumption given by the clk API, but only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * happens to be true with the clk drivers used for Ingenic SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Right now, there is no alternative as the clk API does not have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * round-down function (and won't have one for a while), but if it ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * comes to light, a round-down function should be used instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) rate = clk_round_rate(clk, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (rate < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(chip->dev, "Unable to round rate: %ld", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Calculate period value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tmp = (unsigned long long)rate * state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) do_div(tmp, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) period = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Calculate duty value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tmp = (unsigned long long)rate * state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) do_div(tmp, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) duty = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (duty >= period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) duty = period - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) jz4740_pwm_disable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) err = clk_set_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(chip->dev, "Unable to set rate: %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Reset counter to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Set duty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Set period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Set abrupt shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Set polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * The PWM starts in inactive state until the internal timer reaches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * duty value, then becomes active until the timer reaches the period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * value. In theory, we should then use (period - duty) as the real duty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * value, as a high duty value would otherwise result in the PWM pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * being inactive most of the time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Here, we don't do that, and instead invert the polarity of the PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * when it is active. This trick makes the PWM start with its active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * state instead of its inactive state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) TCU_TCSR_PWM_INITL_HIGH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) TCU_TCSR_PWM_INITL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) TCU_TCSR_PWM_INITL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) jz4740_pwm_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct pwm_ops jz4740_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .request = jz4740_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .free = jz4740_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .apply = jz4740_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int jz4740_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct jz4740_pwm_chip *jz4740;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const struct soc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) info = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!jz4740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) jz4740->map = device_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (IS_ERR(jz4740->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz4740->map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return PTR_ERR(jz4740->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) jz4740->chip.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) jz4740->chip.ops = &jz4740_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) jz4740->chip.npwm = info->num_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) jz4740->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) jz4740->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) jz4740->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) platform_set_drvdata(pdev, jz4740);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return pwmchip_add(&jz4740->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int jz4740_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return pwmchip_remove(&jz4740->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct soc_info __maybe_unused jz4740_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .num_pwms = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct soc_info __maybe_unused jz4725b_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .num_pwms = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct of_device_id jz4740_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct platform_driver jz4740_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .name = "jz4740-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .probe = jz4740_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .remove = jz4740_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) module_platform_driver(jz4740_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_ALIAS("platform:jz4740-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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