^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * simple driver for PWM (Pulse Width Modulator) controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - When disabled the output is driven to 0 independent of the configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MX3_PWMCR 0x00 /* PWM Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MX3_PWMSR 0x04 /* PWM Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MX3_PWMSAR 0x0C /* PWM Sample Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MX3_PWMPR 0x10 /* PWM Period Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MX3_PWMCR_FWM GENMASK(27, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MX3_PWMCR_STOPEN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MX3_PWMCR_DOZEN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MX3_PWMCR_WAITEN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MX3_PWMCR_DBGEN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MX3_PWMCR_BCTR BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MX3_PWMCR_HCTR BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MX3_PWMCR_POUTC GENMASK(19, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MX3_PWMCR_POUTC_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MX3_PWMCR_POUTC_INVERTED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MX3_PWMCR_POUTC_OFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MX3_PWMCR_CLKSRC GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MX3_PWMCR_CLKSRC_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MX3_PWMCR_CLKSRC_IPG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MX3_PWMCR_CLKSRC_IPG_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MX3_PWMCR_CLKSRC_IPG_32K 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MX3_PWMCR_PRESCALER GENMASK(15, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MX3_PWMCR_SWR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MX3_PWMCR_REPEAT GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MX3_PWMCR_REPEAT_1X 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MX3_PWMCR_REPEAT_2X 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MX3_PWMCR_REPEAT_4X 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MX3_PWMCR_REPEAT_8X 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MX3_PWMCR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MX3_PWMSR_FWE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MX3_PWMSR_CMP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MX3_PWMSR_ROV BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MX3_PWMSR_FE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MX3_PWMSR_FIFOAV GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MX3_PWMSR_FIFOAV_EMPTY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MX3_PWMSR_FIFOAV_1WORD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MX3_PWMSR_FIFOAV_2WORDS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MX3_PWMSR_FIFOAV_3WORDS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MX3_PWMSR_FIFOAV_4WORDS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (x)) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MX3_PWM_SWR_LOOP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* PWMPR register value of 0xffff has the same effect as 0xfffe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MX3_PWMPR_MAX 0xfffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pwm_imx27_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * The driver cannot read the current duty cycle from the hardware if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * the hardware is disabled. Cache the last programmed duty cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * value to return in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = clk_prepare_enable(imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = clk_prepare_enable(imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk_disable_unprepare(imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk_disable_unprepare(imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clk_disable_unprepare(imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void pwm_imx27_get_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pwm_device *pwm, struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 period, prescaler, pwm_clk, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = pwm_imx27_clk_prepare_enable(imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) val = readl(imx->mmio_base + MX3_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (val & MX3_PWMCR_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case MX3_PWMCR_POUTC_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case MX3_PWMCR_POUTC_INVERTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) state->polarity = PWM_POLARITY_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_warn(chip->dev, "can't set polarity, output disconnected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) prescaler = MX3_PWMCR_PRESCALER_GET(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pwm_clk = clk_get_rate(imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = readl(imx->mmio_base + MX3_PWMPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * use the cached value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val = readl(imx->mmio_base + MX3_PWMSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val = imx->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pwm_imx27_clk_disable_unprepare(imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void pwm_imx27_sw_reset(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct device *dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int wait_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) usleep_range(200, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cr = readl(imx->mmio_base + MX3_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } while ((cr & MX3_PWMCR_SWR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (wait_count++ < MX3_PWM_SWR_LOOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (cr & MX3_PWMCR_SWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_warn(dev, "software reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct device *dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int period_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int fifoav;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sr = readl(imx->mmio_base + MX3_PWMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) NSEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) msleep(period_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) sr = readl(imx->mmio_base + MX3_PWMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_warn(dev, "there is no free FIFO slot\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned long period_cycles, duty_cycles, prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct pwm_state cstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long long clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pwm_get_state(pwm, &cstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clkrate = clk_get_rate(imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) c = clkrate * state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) do_div(c, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) period_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) prescale = period_cycles / 0x10000 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) period_cycles /= prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) c = clkrate * state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) do_div(c, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) duty_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) duty_cycles /= prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * according to imx pwm RM, the real period value should be PERIOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * value in PWMPR plus 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (period_cycles > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) period_cycles -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) period_cycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Wait for a free FIFO slot if the PWM is already enabled, and flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * the FIFO if the PWM was disabled and is about to be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (cstate.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pwm_imx27_wait_fifo_slot(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = pwm_imx27_clk_prepare_enable(imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pwm_imx27_sw_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel(period_cycles, imx->mmio_base + MX3_PWMPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Store the duty cycle for future reference in cases where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) imx->duty_cycle = duty_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cr = MX3_PWMCR_PRESCALER_SET(prescale) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MX3_PWMCR_DBGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (state->polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cr |= FIELD_PREP(MX3_PWMCR_POUTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MX3_PWMCR_POUTC_INVERTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cr |= MX3_PWMCR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(cr, imx->mmio_base + MX3_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pwm_imx27_clk_disable_unprepare(imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct pwm_ops pwm_imx27_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .apply = pwm_imx27_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .get_state = pwm_imx27_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct of_device_id pwm_imx27_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { .compatible = "fsl,imx27-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int pwm_imx27_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct pwm_imx27_chip *imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 pwmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (imx == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) platform_set_drvdata(pdev, imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (IS_ERR(imx->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret = PTR_ERR(imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "getting ipg clock failed with %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) imx->clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (IS_ERR(imx->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret = PTR_ERR(imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "failed to get peripheral clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) imx->chip.ops = &pwm_imx27_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) imx->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) imx->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) imx->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) imx->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) imx->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (IS_ERR(imx->mmio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return PTR_ERR(imx->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = pwm_imx27_clk_prepare_enable(imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* keep clks on if pwm is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pwmcr = readl(imx->mmio_base + MX3_PWMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!(pwmcr & MX3_PWMCR_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pwm_imx27_clk_disable_unprepare(imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return pwmchip_add(&imx->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int pwm_imx27_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct pwm_imx27_chip *imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) imx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return pwmchip_remove(&imx->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct platform_driver imx_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "pwm-imx27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .of_match_table = pwm_imx27_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .probe = pwm_imx27_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .remove = pwm_imx27_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) module_platform_driver(imx_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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