^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * simple driver for PWM (Pulse Width Modulator) controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MX1_PWMC 0x00 /* PWM Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MX1_PWMS 0x04 /* PWM Sample Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MX1_PWMP 0x08 /* PWM Period Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MX1_PWMC_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct pwm_imx1_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define to_pwm_imx1_chip(chip) container_of(chip, struct pwm_imx1_chip, chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int pwm_imx1_clk_prepare_enable(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ret = clk_prepare_enable(imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = clk_prepare_enable(imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clk_disable_unprepare(imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void pwm_imx1_clk_disable_unprepare(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clk_disable_unprepare(imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clk_disable_unprepare(imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int pwm_imx1_config(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pwm_device *pwm, int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 max, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * The PWM subsystem allows for exact frequencies. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * I cannot connect a scope on my device to the PWM line and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * thus cannot provide the program the PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * exactly. Instead, I'm relying on the fact that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Bootloader (u-boot or WinCE+haret) has programmed the PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * function group already. So I'll just modify the PWM sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * register to follow the ratio of duty_ns vs. period_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * This is good enough for programming the brightness of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * the LCD backlight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * The real implementation would divide PERCLK[0] first by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * both the prescaler (/1 .. /128) and then by CLKSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * (/2 .. /16).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) max = readl(imx->mmio_base + MX1_PWMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) p = max * duty_ns / period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(max - p, imx->mmio_base + MX1_PWMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int pwm_imx1_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = pwm_imx1_clk_prepare_enable(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) value = readl(imx->mmio_base + MX1_PWMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) value |= MX1_PWMC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(value, imx->mmio_base + MX1_PWMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void pwm_imx1_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) value = readl(imx->mmio_base + MX1_PWMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) value &= ~MX1_PWMC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(value, imx->mmio_base + MX1_PWMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pwm_imx1_clk_disable_unprepare(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct pwm_ops pwm_imx1_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .enable = pwm_imx1_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .disable = pwm_imx1_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .config = pwm_imx1_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct of_device_id pwm_imx1_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .compatible = "fsl,imx1-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MODULE_DEVICE_TABLE(of, pwm_imx1_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int pwm_imx1_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct pwm_imx1_chip *imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) platform_set_drvdata(pdev, imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (IS_ERR(imx->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PTR_ERR(imx->clk_ipg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return PTR_ERR(imx->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) imx->clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (IS_ERR(imx->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ret = PTR_ERR(imx->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "failed to get peripheral clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) imx->chip.ops = &pwm_imx1_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) imx->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) imx->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) imx->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (IS_ERR(imx->mmio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return PTR_ERR(imx->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return pwmchip_add(&imx->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int pwm_imx1_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct pwm_imx1_chip *imx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return pwmchip_remove(&imx->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct platform_driver pwm_imx1_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "pwm-imx1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .of_match_table = pwm_imx1_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .probe = pwm_imx1_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .remove = pwm_imx1_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) module_platform_driver(pwm_imx1_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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