Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2018-2019 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * - The TPM counter and period counter are shared between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   multiple channels, so all channels should use same period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *   settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * - Changes to polarity cannot be latched at the time of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *   next period start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * - Changing period and duty cycle together isn't atomic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *   with the wrong timing it might happen that a period is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *   produced with old duty cycle but new period settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PWM_IMX_TPM_PARAM	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PWM_IMX_TPM_GLOBAL	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PWM_IMX_TPM_SC		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PWM_IMX_TPM_CNT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PWM_IMX_TPM_MOD		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PWM_IMX_TPM_CnSC(n)	(0x20 + (n) * 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PWM_IMX_TPM_CnV(n)	(0x24 + (n) * 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PWM_IMX_TPM_PARAM_CHAN			GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PWM_IMX_TPM_SC_PS			GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PWM_IMX_TPM_SC_CMOD			GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK	FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PWM_IMX_TPM_SC_CPWMS			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PWM_IMX_TPM_CnSC_CHF	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PWM_IMX_TPM_CnSC_MSB	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PWM_IMX_TPM_CnSC_MSA	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * The reference manual describes this field as two separate bits. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * semantic of the two bits isn't orthogonal though, so they are treated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * together as a 2-bit field here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PWM_IMX_TPM_CnSC_ELS	GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PWM_IMX_TPM_CnSC_ELS_INVERSED	FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PWM_IMX_TPM_CnSC_ELS_NORMAL	FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PWM_IMX_TPM_MOD_WIDTH	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PWM_IMX_TPM_MOD_MOD	GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct imx_tpm_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u32 user_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 enable_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 real_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct imx_tpm_pwm_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static inline struct imx_tpm_pwm_chip *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) to_imx_tpm_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return container_of(chip, struct imx_tpm_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * This function determines for a given pwm_state *state that a consumer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * might request the pwm_state *real_state that eventually is implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * by the hardware and the necessary register values (in *p) to achieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 				   struct imx_tpm_pwm_param *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				   struct pwm_state *real_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				   const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 rate, prescale, period_count, clock_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	rate = clk_get_rate(tpm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	tmp = (u64)state->period * rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (clock_unit <= PWM_IMX_TPM_MOD_MOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		prescale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	p->prescale = prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	p->mod = period_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* calculate real period HW can support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	tmp = (u64)period_count << prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	tmp *= NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * if eventually the PWM output is inactive, either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * duty cycle is 0 or status is disabled, need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * make sure the output pin is inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (!state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		real_state->duty_cycle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		real_state->duty_cycle = state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	tmp = (u64)p->mod * real_state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	real_state->polarity = state->polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	real_state->enabled = state->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void pwm_imx_tpm_get_state(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				  struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				  struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u32 rate, val, prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* get period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	state->period = tpm->real_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* get duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	rate = clk_get_rate(tpm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	val = readl(tpm->base + PWM_IMX_TPM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tmp = (tmp << prescale) * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* get polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		state->polarity = PWM_POLARITY_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		 * Assume reserved values (2b00 and 2b11) to yield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		 * normal polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* get channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* this function is supposed to be called with mutex hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				struct imx_tpm_pwm_param *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				struct pwm_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	bool period_update = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	bool duty_update = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u32 val, cmod, cur_prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct pwm_state c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (state->period != tpm->real_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		 * TPM counter is shared by multiple channels, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		 * prescale and period can NOT be modified when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		 * there are multiple channels in use with different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		 * period settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		if (tpm->user_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		val = readl(tpm->base + PWM_IMX_TPM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		if (cmod && cur_prescale != p->prescale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		/* set TPM counter prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		val &= ~PWM_IMX_TPM_SC_PS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		writel(val, tpm->base + PWM_IMX_TPM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		 * set period count:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		 * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		 * is updated when MOD register is written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		 * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		 * is latched into hardware when the next period starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		tpm->real_period = state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		period_update = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	pwm_imx_tpm_get_state(chip, pwm, &c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* polarity is NOT allowed to be changed if PWM is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (c.enabled && c.polarity != state->polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (state->duty_cycle != c.duty_cycle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		 * set channel value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		 * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		 * is updated when CnV register is written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		 * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the duty length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		 * is latched into hardware when the next period starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		duty_update = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/* make sure MOD & CnV registers are updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (period_update || duty_update) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		timeout = jiffies + msecs_to_jiffies(tpm->real_period /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 						     NSEC_PER_MSEC + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		       || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		       != p->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * polarity settings will enabled/disable output status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 * immediately, so if the channel is disabled, need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 * make sure MSA/MSB/ELS are set to 0 which means channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		 PWM_IMX_TPM_CnSC_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		 * set polarity (for edge-aligned PWM modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		 * ELS[1:0] = 2b10 yields normal polarity behaviour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		 * ELS[1:0] = 2b01 yields inversed polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		 * The other values are reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		val |= PWM_IMX_TPM_CnSC_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		val |= (state->polarity == PWM_POLARITY_NORMAL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			PWM_IMX_TPM_CnSC_ELS_NORMAL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			PWM_IMX_TPM_CnSC_ELS_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* control the counter status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (state->enabled != c.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		val = readl(tpm->base + PWM_IMX_TPM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		if (state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			if (++tpm->enable_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			if (--tpm->enable_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				val &= ~PWM_IMX_TPM_SC_CMOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		writel(val, tpm->base + PWM_IMX_TPM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int pwm_imx_tpm_apply(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			     struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			     const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct imx_tpm_pwm_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct pwm_state real_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	ret = pwm_imx_tpm_round_state(chip, &param, &real_state, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	mutex_lock(&tpm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	ret = pwm_imx_tpm_apply_hw(chip, &param, &real_state, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	mutex_unlock(&tpm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	mutex_lock(&tpm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	tpm->user_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	mutex_unlock(&tpm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	mutex_lock(&tpm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	tpm->user_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	mutex_unlock(&tpm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct pwm_ops imx_tpm_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.request = pwm_imx_tpm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.free = pwm_imx_tpm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.get_state = pwm_imx_tpm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.apply = pwm_imx_tpm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int pwm_imx_tpm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct imx_tpm_pwm_chip *tpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	tpm = devm_kzalloc(&pdev->dev, sizeof(*tpm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (!tpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	platform_set_drvdata(pdev, tpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	tpm->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (IS_ERR(tpm->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return PTR_ERR(tpm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	tpm->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (IS_ERR(tpm->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		ret = PTR_ERR(tpm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				"failed to get PWM clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	ret = clk_prepare_enable(tpm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			"failed to prepare or enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	tpm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	tpm->chip.ops = &imx_tpm_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	tpm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	tpm->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	tpm->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	/* get number of channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	val = readl(tpm->base + PWM_IMX_TPM_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	mutex_init(&tpm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	ret = pwmchip_add(&tpm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		clk_disable_unprepare(tpm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int pwm_imx_tpm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	struct imx_tpm_pwm_chip *tpm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	int ret = pwmchip_remove(&tpm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	clk_disable_unprepare(tpm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int __maybe_unused pwm_imx_tpm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (tpm->enable_count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	clk_disable_unprepare(tpm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int __maybe_unused pwm_imx_tpm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	ret = clk_prepare_enable(tpm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			"failed to prepare or enable clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			 pwm_imx_tpm_suspend, pwm_imx_tpm_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct of_device_id imx_tpm_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	{ .compatible = "fsl,imx7ulp-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct platform_driver imx_tpm_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		.name = "imx7ulp-tpm-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		.of_match_table = imx_tpm_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		.pm = &imx_tpm_pwm_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.probe	= pwm_imx_tpm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.remove = pwm_imx_tpm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) module_platform_driver(imx_tpm_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_DESCRIPTION("i.MX TPM PWM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_LICENSE("GPL v2");