^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Imagination Technologies Pulse Width Modulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014-2015, Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* PWM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWM_CTRL_CFG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWM_CTRL_CFG_NO_SUB_DIV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PWM_CTRL_CFG_SUB_DIV0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWM_CTRL_CFG_SUB_DIV1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PWM_CTRL_CFG_DIV_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PWM_CH_CFG_TMBASE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PWM_CH_CFG_DUTY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PERIP_PWM_PDM_CONTROL 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMG_PWM_PM_TIMEOUT 1000 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * PWM period is specified with a timebase register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * in number of step periods. The PWM duty cycle is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * specified in step periods, in the [0, $timebase] range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * In other words, the timebase imposes the duty cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * resolution. Therefore, let's constraint the timebase to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * a minimum value to allow a sane range of duty cycle values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Imposing a minimum timebase, will impose a maximum PWM frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The value chosen is completely arbitrary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MIN_TMBASE_STEPS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMG_PWM_NPWM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct img_pwm_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 max_timebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct img_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct clk *pwm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct regmap *periph_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int max_period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int min_period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const struct img_pwm_soc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 suspend_ctrl_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 suspend_ch_cfg[IMG_PWM_NPWM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return container_of(chip, struct img_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline void img_pwm_writel(struct img_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(val, chip->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return readl(chip->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 val, div, duty, timebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long mul, output_clk_hz, input_clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int max_timebase = pwm_chip->data->max_timebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (period_ns < pwm_chip->min_period_ns ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) period_ns > pwm_chip->max_period_ns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_err(chip->dev, "configured period not in range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (mul <= max_timebase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) div = PWM_CTRL_CFG_NO_SUB_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) timebase = DIV_ROUND_UP(mul, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } else if (mul <= max_timebase * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) div = PWM_CTRL_CFG_SUB_DIV0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) timebase = DIV_ROUND_UP(mul, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } else if (mul <= max_timebase * 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) div = PWM_CTRL_CFG_SUB_DIV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) timebase = DIV_ROUND_UP(mul, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } else if (mul <= max_timebase * 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) timebase = DIV_ROUND_UP(mul, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "failed to configure timebase steps/divider value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = pm_runtime_get_sync(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pm_runtime_put_autosuspend(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (timebase << PWM_CH_CFG_TMBASE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pm_runtime_mark_last_busy(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pm_runtime_put_autosuspend(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = pm_runtime_resume_and_get(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val |= BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PERIP_PWM_PDM_CONTROL_CH_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val &= ~BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pm_runtime_mark_last_busy(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pm_runtime_put_autosuspend(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct pwm_ops img_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .config = img_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .enable = img_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .disable = img_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct img_pwm_soc_data pistachio_pwm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .max_timebase = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct of_device_id img_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .compatible = "img,pistachio-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .data = &pistachio_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MODULE_DEVICE_TABLE(of, img_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int img_pwm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clk_disable_unprepare(pwm_chip->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clk_disable_unprepare(pwm_chip->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int img_pwm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = clk_prepare_enable(pwm_chip->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(dev, "could not prepare or enable sys clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = clk_prepare_enable(pwm_chip->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(dev, "could not prepare or enable pwm clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_disable_unprepare(pwm_chip->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int img_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct img_pwm_chip *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) const struct of_device_id *of_dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pwm->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pwm->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (IS_ERR(pwm->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return PTR_ERR(pwm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!of_dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pwm->data = of_dev_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "img,cr-periph");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (IS_ERR(pwm->periph_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return PTR_ERR(pwm->periph_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (IS_ERR(pwm->sys_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_err(&pdev->dev, "failed to get system clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return PTR_ERR(pwm->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (IS_ERR(pwm->pwm_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(&pdev->dev, "failed to get pwm clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return PTR_ERR(pwm->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) platform_set_drvdata(pdev, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = img_pwm_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clk_rate = clk_get_rate(pwm->pwm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(&pdev->dev, "pwm clock has no frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* The maximum input clock divider is 512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) do_div(val, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pwm->max_period_ns = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) do_div(val, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pwm->min_period_ns = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pwm->chip.ops = &img_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pwm->chip.npwm = IMG_PWM_NPWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = pwmchip_add(&pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!pm_runtime_enabled(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) img_pwm_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int img_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) img_pwm_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return pwmchip_remove(&pwm_chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int img_pwm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = img_pwm_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) for (i = 0; i < pwm_chip->chip.npwm; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PWM_CH_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) img_pwm_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int img_pwm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = img_pwm_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) for (i = 0; i < pwm_chip->chip.npwm; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) img_pwm_writel(pwm_chip, PWM_CH_CFG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pwm_chip->suspend_ch_cfg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for (i = 0; i < pwm_chip->chip.npwm; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (pwm_chip->suspend_ctrl_cfg & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) regmap_update_bits(pwm_chip->periph_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PERIP_PWM_PDM_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PERIP_PWM_PDM_CONTROL_CH_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) img_pwm_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct dev_pm_ops img_pwm_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) img_pwm_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct platform_driver img_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .name = "img-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .pm = &img_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .of_match_table = img_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .probe = img_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .remove = img_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) module_platform_driver(img_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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