^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PWM Controller Driver for HiSilicon BVT SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PWM_ENABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWM_ENABLE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PWM_POLARITY_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWM_POLARITY_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PWM_KEEP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PWM_KEEP_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PWM_PERIOD_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PWM_DUTY_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct hibvt_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) const struct hibvt_pwm_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct hibvt_pwm_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 num_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bool quirk_force_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct hibvt_pwm_soc hi3516cv300_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .num_pwms = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct hibvt_pwm_soc hi3519v100_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .num_pwms = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct hibvt_pwm_soc hi3559v100_shub_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .num_pwms = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .quirk_force_enable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct hibvt_pwm_soc hi3559v100_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .num_pwms = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .quirk_force_enable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return container_of(chip, struct hibvt_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void __iomem *address = base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) value = readl(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) value |= (data & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writel(value, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PWM_ENABLE_MASK, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PWM_ENABLE_MASK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int duty_cycle_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 freq, period, duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) period = div_u64(freq * period_ns, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) duty = div_u64(period * duty_cycle_ns, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PWM_PERIOD_MASK, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PWM_DUTY_MASK, duty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 freq, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) base = hi_pwm_chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) state->period = div_u64(value * 1000, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) state->duty_cycle = div_u64(value * 1000, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) state->enabled = (PWM_ENABLE_MASK & value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (state->polarity != pwm->state.polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) hibvt_pwm_set_polarity(chip, pwm, state->polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (state->period != pwm->state.period ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) state->duty_cycle != pwm->state.duty_cycle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Some implementations require the PWM to be enabled twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * each time the duty cycle is refreshed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (hi_pwm_chip->soc->quirk_force_enable && state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) hibvt_pwm_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (state->enabled != pwm->state.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) hibvt_pwm_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) hibvt_pwm_disable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct pwm_ops hibvt_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .get_state = hibvt_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .apply = hibvt_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int hibvt_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const struct hibvt_pwm_soc *soc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct hibvt_pwm_chip *pwm_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (pwm_chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (IS_ERR(pwm_chip->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(&pdev->dev, "getting clock failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PTR_ERR(pwm_chip->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return PTR_ERR(pwm_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pwm_chip->chip.ops = &hibvt_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pwm_chip->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pwm_chip->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pwm_chip->chip.npwm = soc->num_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pwm_chip->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pwm_chip->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pwm_chip->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pwm_chip->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (IS_ERR(pwm_chip->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return PTR_ERR(pwm_chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = clk_prepare_enable(pwm_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(pwm_chip->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clk_disable_unprepare(pwm_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return PTR_ERR(pwm_chip->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reset_control_assert(pwm_chip->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) reset_control_deassert(pwm_chip->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = pwmchip_add(&pwm_chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk_disable_unprepare(pwm_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for (i = 0; i < pwm_chip->chip.npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) platform_set_drvdata(pdev, pwm_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int hibvt_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct hibvt_pwm_chip *pwm_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pwm_chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) reset_control_assert(pwm_chip->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reset_control_deassert(pwm_chip->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clk_disable_unprepare(pwm_chip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return pwmchip_remove(&pwm_chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct of_device_id hibvt_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { .compatible = "hisilicon,hi3516cv300-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .data = &hi3516cv300_soc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .compatible = "hisilicon,hi3519v100-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .data = &hi3519v100_soc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .compatible = "hisilicon,hi3559v100-shub-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .data = &hi3559v100_shub_soc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { .compatible = "hisilicon,hi3559v100-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .data = &hi3559v100_soc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct platform_driver hibvt_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "hibvt-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .of_match_table = hibvt_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .probe = hibvt_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .remove = hibvt_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) module_platform_driver(hibvt_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_AUTHOR("Jian Yuan");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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