^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale FlexTimer Module (FTM) PWM Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012-2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/fsl/ftm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum fsl_pwm_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FSL_PWM_CLK_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FSL_PWM_CLK_FIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FSL_PWM_CLK_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) FSL_PWM_CLK_CNTEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FSL_PWM_CLK_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct fsl_ftm_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bool has_enable_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct fsl_pwm_periodcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum fsl_pwm_clk clk_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int clk_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int mod_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct fsl_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* This value is valid iff a pwm is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct fsl_pwm_periodcfg period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk *ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk *clk[FSL_PWM_CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct fsl_ftm_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return container_of(chip, struct fsl_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_read(fpc->regmap, FTM_FMS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (val & FTM_FMS_WPEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FTM_MODE_WPDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct fsl_pwm_periodcfg *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (a->clk_select != b->clk_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (a->clk_ps != b->clk_ps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (a->mod_period != b->mod_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = clk_prepare_enable(fpc->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!ret && fpc->soc->has_enable_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mutex_lock(&fpc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) BIT(pwm->hwpwm + 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mutex_unlock(&fpc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (fpc->soc->has_enable_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mutex_lock(&fpc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mutex_unlock(&fpc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clk_disable_unprepare(fpc->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long long exval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) exval = ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) exval *= 1000000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) do_div(exval, rate >> fpc->period.clk_ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return exval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int period_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum fsl_pwm_clk index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct fsl_pwm_periodcfg *periodcfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) c = clk_get_rate(fpc->clk[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) c = c * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) do_div(c, 1000000000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (c == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (c <= 0x10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) periodcfg->clk_select = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) periodcfg->clk_ps = ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) periodcfg->mod_period = c - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int period_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct fsl_pwm_periodcfg *periodcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum fsl_pwm_clk m0, m1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned long fix_rate, ext_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) periodcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (fix_rate > ext_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) m0 = FSL_PWM_CLK_FIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) m1 = FSL_PWM_CLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) m0 = FSL_PWM_CLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) m1 = FSL_PWM_CLK_FIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int duty_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long long duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int period = fpc->period.mod_period + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) duty = (unsigned long long)duty_ns * period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) do_div(duty, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return (unsigned int)duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) regmap_read(fpc->regmap, FTM_OUTMASK, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (~val & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) regmap_read(fpc->regmap, FTM_OUTMASK, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (~(val | BIT(pwm->hwpwm)) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) const struct pwm_state *newstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 reg_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct fsl_pwm_periodcfg periodcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) bool do_write_period = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(fpc->chip.dev, "failed to calculate new period\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) do_write_period = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * The Freescale FTM controller supports only a single period for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * all PWM channels, therefore verify if the newly computed period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * is different than the current period being used. In such case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * we allow to change the period only if no other pwm is running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(fpc->chip.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "Cannot change period for PWM %u, disable other PWMs first\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (fpc->period.clk_select != periodcfg.clk_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum fsl_pwm_clk oldclk = fpc->period.clk_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) enum fsl_pwm_clk newclk = periodcfg.clk_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = clk_prepare_enable(fpc->clk[newclk]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clk_disable_unprepare(fpc->clk[oldclk]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) do_write_period = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ftm_clear_write_protection(fpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (do_write_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FTM_SC_CLK(periodcfg.clk_select));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) periodcfg.clk_ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) fpc->period = periodcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FTM_CSC_MSB | FTM_CSC_ELSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) reg_polarity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (newstate->polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) reg_polarity = BIT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ftm_set_write_protection(fpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) const struct pwm_state *newstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct pwm_state *oldstate = &pwm->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * oldstate to newstate : action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * disabled to disabled : ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * enabled to disabled : disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * enabled to enabled : update settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * disabled to enabled : update settings + enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mutex_lock(&fpc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!newstate->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (oldstate->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) regmap_update_bits(fpc->regmap, FTM_OUTMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) BIT(pwm->hwpwm), BIT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto end_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = fsl_pwm_apply_config(fpc, pwm, newstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto end_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* check if need to enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!oldstate->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto end_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) goto end_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) end_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mutex_unlock(&fpc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct pwm_ops fsl_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .request = fsl_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .free = fsl_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .apply = fsl_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = clk_prepare_enable(fpc->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) clk_disable_unprepare(fpc->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case FTM_FMS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case FTM_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case FTM_CNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct regmap_config fsl_pwm_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .max_register = FTM_PWMLOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .volatile_reg = fsl_pwm_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int fsl_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct fsl_pwm_chip *fpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!fpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mutex_init(&fpc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) fpc->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) fpc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) &fsl_pwm_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (IS_ERR(fpc->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return PTR_ERR(fpc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) fpc->clk[FSL_PWM_CLK_CNTEN] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * ipg_clk is the interface clock for the IP. If not provided, use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * ftm_sys clock as the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (IS_ERR(fpc->ipg_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) fpc->chip.ops = &fsl_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) fpc->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) fpc->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) fpc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) fpc->chip.npwm = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = pwmchip_add(&fpc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) platform_set_drvdata(pdev, fpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return fsl_pwm_init(fpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int fsl_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return pwmchip_remove(&fpc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int fsl_pwm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) regcache_cache_only(fpc->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) regcache_mark_dirty(fpc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) for (i = 0; i < fpc->chip.npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct pwm_device *pwm = &fpc->chip.pwms[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!test_bit(PWMF_REQUESTED, &pwm->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) clk_disable_unprepare(fpc->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int fsl_pwm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) for (i = 0; i < fpc->chip.npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct pwm_device *pwm = &fpc->chip.pwms[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!test_bit(PWMF_REQUESTED, &pwm->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) clk_prepare_enable(fpc->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* restore all registers from cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) regcache_cache_only(fpc->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) regcache_sync(fpc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct dev_pm_ops fsl_pwm_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct fsl_ftm_soc vf610_ftm_pwm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .has_enable_bits = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .has_enable_bits = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct of_device_id fsl_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static struct platform_driver fsl_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .name = "fsl-ftm-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .of_match_table = fsl_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .pm = &fsl_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .probe = fsl_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .remove = fsl_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) module_platform_driver(fsl_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MODULE_ALIAS("platform:fsl-ftm-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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