^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PWM framework driver for Cirrus Logic EP93xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009 Matthieu Crapet <mcrapet@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2009, 2013 H Hartley Sweeten <hsweeten@visionengravers.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * EP9301/02 have only one channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * EP9307 has only one channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * platform device ep93xx-pwm.0 - PWMOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * EP9312/15 have two channels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * platform device ep93xx-pwm.0 - PWMOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/soc/cirrus/ep93xx.h> /* for ep93xx_pwm_{acquire,release}_gpio() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EP93XX_PWMx_TERM_COUNT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EP93XX_PWMx_DUTY_CYCLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EP93XX_PWMx_ENABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EP93XX_PWMx_INVERT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ep93xx_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline struct ep93xx_pwm *to_ep93xx_pwm(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return container_of(chip, struct ep93xx_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int ep93xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct platform_device *pdev = to_platform_device(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return ep93xx_pwm_acquire_gpio(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void ep93xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct platform_device *pdev = to_platform_device(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ep93xx_pwm_release_gpio(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int ep93xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *base = ep93xx_pwm->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long long c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long period_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long duty_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * The clock needs to be enabled to access the PWM registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Configuration can be changed at any time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = clk_enable(ep93xx_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) c = clk_get_rate(ep93xx_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) c *= period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) do_div(c, 1000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) period_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) c = period_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) c *= duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) do_div(c, period_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) duty_cycles = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (period_cycles < 0x10000 && duty_cycles < 0x10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) term = readw(base + EP93XX_PWMx_TERM_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Order is important if PWM is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (period_cycles > term) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk_disable(ep93xx_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int ep93xx_pwm_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * The clock needs to be enabled to access the PWM registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Polarity can only be changed when the PWM is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = clk_enable(ep93xx_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk_disable(ep93xx_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int ep93xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = clk_enable(ep93xx_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void ep93xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ep93xx_pwm *ep93xx_pwm = to_ep93xx_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clk_disable(ep93xx_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct pwm_ops ep93xx_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .request = ep93xx_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .free = ep93xx_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .config = ep93xx_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .set_polarity = ep93xx_pwm_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .enable = ep93xx_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .disable = ep93xx_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int ep93xx_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct ep93xx_pwm *ep93xx_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ep93xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*ep93xx_pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!ep93xx_pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ep93xx_pwm->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (IS_ERR(ep93xx_pwm->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return PTR_ERR(ep93xx_pwm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ep93xx_pwm->clk = devm_clk_get(&pdev->dev, "pwm_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (IS_ERR(ep93xx_pwm->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return PTR_ERR(ep93xx_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ep93xx_pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ep93xx_pwm->chip.ops = &ep93xx_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ep93xx_pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ep93xx_pwm->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = pwmchip_add(&ep93xx_pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) platform_set_drvdata(pdev, ep93xx_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int ep93xx_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct ep93xx_pwm *ep93xx_pwm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return pwmchip_remove(&ep93xx_pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct platform_driver ep93xx_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "ep93xx-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .probe = ep93xx_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .remove = ep93xx_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) module_platform_driver(ep93xx_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_DESCRIPTION("Cirrus Logic EP93xx PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MODULE_AUTHOR("Matthieu Crapet <mcrapet@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MODULE_AUTHOR("H Hartley Sweeten <hsweeten@visionengravers.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MODULE_ALIAS("platform:ep93xx-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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