^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Expose a PWM controlled by the ChromeOS EC to the host processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_data/cros_ec_commands.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_data/cros_ec_proto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * struct cros_ec_pwm_device - Driver data for EC PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @dev: Device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @ec: Pointer to EC device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @chip: PWM controller chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct cros_ec_pwm_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct cros_ec_device *ec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * struct cros_ec_pwm - per-PWM driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @duty_cycle: cached duty cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct cros_ec_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u16 duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return container_of(c, struct cros_ec_pwm_device, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int cros_ec_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct cros_ec_pwm *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) channel = kzalloc(sizeof(*channel), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (!channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pwm_set_chip_data(pwm, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) kfree(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct cros_ec_command msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct ec_params_pwm_set_duty params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } __packed buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ec_params_pwm_set_duty *params = &buf.params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct cros_ec_command *msg = &buf.msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) memset(&buf, 0, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) msg->version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) msg->command = EC_CMD_PWM_SET_DUTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) msg->insize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) msg->outsize = sizeof(*params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) params->duty = duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) params->pwm_type = EC_PWM_TYPE_GENERIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) params->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return cros_ec_cmd_xfer_status(ec, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct cros_ec_command msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct ec_params_pwm_get_duty params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct ec_response_pwm_get_duty resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } __packed buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct ec_params_pwm_get_duty *params = &buf.params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ec_response_pwm_get_duty *resp = &buf.resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct cros_ec_command *msg = &buf.msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) memset(&buf, 0, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) msg->version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) msg->command = EC_CMD_PWM_GET_DUTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) msg->insize = sizeof(*resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) msg->outsize = sizeof(*params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) params->pwm_type = EC_PWM_TYPE_GENERIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) params->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = cros_ec_cmd_xfer_status(ec, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return resp->duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* The EC won't let us change the period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (state->period != EC_PWM_MAX_DUTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * EC doesn't separate the concept of duty cycle and enabled, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * kernel does. Translate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) duty_cycle = state->enabled ? state->duty_cycle : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) channel->duty_cycle = state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(chip->dev, "error getting initial duty: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) state->enabled = (ret > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) state->period = EC_PWM_MAX_DUTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Note that "disabled" and "duty cycle == 0" are treated the same. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * the cached duty cycle is not zero, used the cached duty cycle. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * ensures that the configured duty cycle is kept across a disable and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * enable operation and avoids potentially confusing consumers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * For the case of the initial hardware readout, channel->duty_cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * will be 0 and the actual duty cycle read from the EC is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret == 0 && channel->duty_cycle > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) state->duty_cycle = channel->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) state->duty_cycle = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct pwm_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cros_ec_pwm_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct pwm_device *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (args->args[0] >= pc->npwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pwm = pwm_request_from_chip(pc, args->args[0], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* The EC won't let us change the period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pwm->args.period = EC_PWM_MAX_DUTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct pwm_ops cros_ec_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .request = cros_ec_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .free = cros_ec_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .get_state = cros_ec_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .apply = cros_ec_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Determine the number of supported PWMs. The EC does not return the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * of PWMs it supports directly, so we have to read the pwm duty cycle for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * subsequent channels until we get an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int cros_ec_num_pwms(struct cros_ec_device *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* The index field is only 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for (i = 0; i <= U8_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = cros_ec_pwm_get_duty(ec, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * responses; everything else is treated as an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * The EC error codes map to -EOPNOTSUPP and -EINVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * so check for those.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case -EOPNOTSUPP: /* invalid command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case -EINVAL: /* invalid parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return U8_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int cros_ec_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct cros_ec_pwm_device *ec_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pwm_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!ec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_err(dev, "no parent EC device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!ec_pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) chip = &ec_pwm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ec_pwm->ec = ec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* PWM chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) chip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) chip->ops = &cros_ec_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) chip->of_xlate = cros_ec_pwm_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) chip->of_pwm_n_cells = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = cros_ec_num_pwms(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(dev, "Couldn't find PWMs: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) chip->npwm = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = pwmchip_add(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(dev, "cannot register PWM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) platform_set_drvdata(pdev, ec_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int cros_ec_pwm_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pwm_chip *chip = &ec_pwm->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return pwmchip_remove(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct of_device_id cros_ec_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { .compatible = "google,cros-ec-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct platform_driver cros_ec_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .probe = cros_ec_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .remove = cros_ec_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "cros-ec-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .of_match_table = of_match_ptr(cros_ec_pwm_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) module_platform_driver(cros_ec_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_ALIAS("platform:cros-ec-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_DESCRIPTION("ChromeOS EC PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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