^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Shobhit Kumar <shobhit.kumar@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/intel_soc_pmic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PWM0_CLK_DIV 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PWM_OUTPUT_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PWM0_DUTY_CYCLE 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BACKLIGHT_EN 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PWM_MAX_LEVEL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * struct crystalcove_pwm - Crystal Cove PWM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @chip: the abstract pwm_chip structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @regmap: the regmap from the parent device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct crystalcove_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return container_of(pc, struct crystalcove_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int crc_pwm_calc_clk_div(int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* clk_div 1 - 128, maps to register values 0-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (clk_div > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clk_div--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct device *dev = crc_pwm->chip.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (state->period > PWM_MAX_PERIOD_NS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dev_err(dev, "un-supported period_ns\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (state->polarity != PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (pwm_is_enabled(pwm) && !state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (pwm_get_duty_cycle(pwm) != state->duty_cycle ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pwm_get_period(pwm) != state->period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u64 level = state->duty_cycle * PWM_MAX_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) do_div(level, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (pwm_is_enabled(pwm) && state->enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pwm_get_period(pwm) != state->period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (pwm_get_period(pwm) != state->period ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pwm_is_enabled(pwm) != state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int clk_div = crc_pwm_calc_clk_div(state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk_div | pwm_output_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!pwm_is_enabled(pwm) && state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct device *dev = crc_pwm->chip.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int clk_div, clk_div_reg, duty_cycle_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) state->period =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) state->duty_cycle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct pwm_ops crc_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .apply = crc_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .get_state = crc_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int crystalcove_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct crystalcove_pwm *pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device *dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pwm->chip.ops = &crc_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pwm->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* get the PMIC regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pwm->regmap = pmic->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) platform_set_drvdata(pdev, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return pwmchip_add(&pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int crystalcove_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct crystalcove_pwm *pwm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return pwmchip_remove(&pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct platform_driver crystalcove_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .probe = crystalcove_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .remove = crystalcove_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .name = "crystal_cove_pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) builtin_platform_driver(crystalcove_pwm_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags