^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PWM_CONTROL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PWM_CONTROL_SHIFT(x) ((x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PWM_CONTROL_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PWM_MODE 0x80 /* set timer in PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PWM_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PWM_POLARITY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PERIOD(x) (((x) * 0x10) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DUTY(x) (((x) * 0x10) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PERIOD_MIN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct bcm2835_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return container_of(chip, struct bcm2835_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) value = readl(pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel(value, pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) value = readl(pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) writel(value, pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long rate = clk_get_rate(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long scaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dev_err(pc->dev, "failed to get clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) scaler = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) period = DIV_ROUND_CLOSEST(period_ns, scaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (period < PERIOD_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writel(DIV_ROUND_CLOSEST(duty_ns, scaler),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pc->base + DUTY(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(period, pc->base + PERIOD(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int bcm2835_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) value = readl(pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(value, pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void bcm2835_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) value = readl(pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(value, pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int bcm2835_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) value = readl(pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (polarity == PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel(value, pc->base + PWM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct pwm_ops bcm2835_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .request = bcm2835_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .free = bcm2835_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .config = bcm2835_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .enable = bcm2835_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .disable = bcm2835_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .set_polarity = bcm2835_set_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int bcm2835_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct bcm2835_pwm *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pc->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (IS_ERR(pc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return PTR_ERR(pc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pc->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (IS_ERR(pc->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = clk_prepare_enable(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pc->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pc->chip.ops = &bcm2835_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pc->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pc->chip.npwm = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pc->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pc->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = pwmchip_add(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) goto add_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) add_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clk_disable_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int bcm2835_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct bcm2835_pwm *pc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk_disable_unprepare(pc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return pwmchip_remove(&pc->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct of_device_id bcm2835_pwm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .compatible = "brcm,bcm2835-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct platform_driver bcm2835_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "bcm2835-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .of_match_table = bcm2835_pwm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .probe = bcm2835_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .remove = bcm2835_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) module_platform_driver(bcm2835_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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