^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * The Kona PWM has some unusual characteristics. Here are the main points.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 1) There is no disable bit and the hardware docs advise programming a zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * duty to achieve output equivalent to that of a normal disable operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 2) Changes to prescale, duty, period, and polarity do not take effect until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * a subsequent rising edge of the trigger bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 3) If the smooth bit and trigger bit are both low, the output is a constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * high signal. Otherwise, the earlier waveform continues to be output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 4) If the smooth bit is set on the rising edge of the trigger bit, output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * will transition to the new settings on a period boundary (which could be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * seconds away). If the smooth bit is clear, new settings will be applied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * as soon as possible (the hardware always has a 400ns delay).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 5) When the external clock that feeds the PWM is disabled, output is pegged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * high or low depending on its state at that exact instant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PWM_CONTROL_OFFSET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PWM_CONTROL_TRIGGER_SHIFT(chan) (chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PRESCALE_OFFSET 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PRESCALE_SHIFT(chan) ((chan) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PRESCALE_MIN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PRESCALE_MAX 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PERIOD_COUNT_MIN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PERIOD_COUNT_MAX 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DUTY_CYCLE_HIGH_MIN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DUTY_CYCLE_HIGH_MAX 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct kona_pwmc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return container_of(_chip, struct kona_pwmc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Clear trigger bit but set smooth bit to maintain old output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(value, kp->base + PWM_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * There must be a min 400ns delay between clearing trigger and setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * it. Failing to do this may result in no PWM signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ndelay(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Set trigger bit and clear smooth bit to apply new settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(value, kp->base + PWM_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Trigger bit must be held high for at least 400 ns. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ndelay(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct kona_pwmc *kp = to_kona_pwmc(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u64 val, div, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long prescale = PRESCALE_MIN, pc, dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int value, chan = pwm->hwpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Find period count, duty count and prescale to suit duty_ns and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * period_ns. This is done according to formulas described below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rate = clk_get_rate(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) div = 1000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) div *= 1 + prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) val = rate * period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pc = div64_u64(val, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val = rate * duty_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dc = div64_u64(val, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* If duty_ns or period_ns are not achievable then return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (pc < PERIOD_COUNT_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* If pc and dc are in bounds, the calculation is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Otherwise, increase prescale and recalculate pc and dc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (++prescale > PRESCALE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Don't apply settings if disabled. The period and duty cycle are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * always calculated above to ensure the new values are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * validated immediately instead of on enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (pwm_is_enabled(pwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) kona_pwmc_prepare_for_settings(kp, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) value = readl(kp->base + PRESCALE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) value &= ~PRESCALE_MASK(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) value |= prescale << PRESCALE_SHIFT(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(value, kp->base + PRESCALE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) kona_pwmc_apply_settings(kp, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct kona_pwmc *kp = to_kona_pwmc(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int chan = pwm->hwpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = clk_prepare_enable(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_err(chip->dev, "failed to enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) kona_pwmc_prepare_for_settings(kp, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) value = readl(kp->base + PWM_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (polarity == PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(value, kp->base + PWM_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) kona_pwmc_apply_settings(kp, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk_disable_unprepare(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct kona_pwmc *kp = to_kona_pwmc(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = clk_prepare_enable(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(chip->dev, "failed to enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = kona_pwmc_config(chip, pwm, pwm_get_duty_cycle(pwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pwm_get_period(pwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk_disable_unprepare(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct kona_pwmc *kp = to_kona_pwmc(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int chan = pwm->hwpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) kona_pwmc_prepare_for_settings(kp, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Simulate a disable by configuring for zero duty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Set prescale to 0 for this channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) value = readl(kp->base + PRESCALE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) value &= ~PRESCALE_MASK(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(value, kp->base + PRESCALE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) kona_pwmc_apply_settings(kp, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clk_disable_unprepare(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct pwm_ops kona_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .config = kona_pwmc_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .set_polarity = kona_pwmc_set_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .enable = kona_pwmc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .disable = kona_pwmc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int kona_pwmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct kona_pwmc *kp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) kp = devm_kzalloc(&pdev->dev, sizeof(*kp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (kp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) platform_set_drvdata(pdev, kp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) kp->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) kp->chip.ops = &kona_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) kp->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) kp->chip.npwm = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) kp->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) kp->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) kp->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (IS_ERR(kp->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return PTR_ERR(kp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) kp->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (IS_ERR(kp->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(&pdev->dev, "failed to get clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PTR_ERR(kp->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return PTR_ERR(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = clk_prepare_enable(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Set push/pull for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) for (chan = 0; chan < kp->chip.npwm; chan++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) writel(value, kp->base + PWM_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clk_disable_unprepare(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = pwmchip_add_with_polarity(&kp->chip, PWM_POLARITY_INVERSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int kona_pwmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct kona_pwmc *kp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) for (chan = 0; chan < kp->chip.npwm; chan++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (pwm_is_enabled(&kp->chip.pwms[chan]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clk_disable_unprepare(kp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return pwmchip_remove(&kp->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct of_device_id bcm_kona_pwmc_dt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .compatible = "brcm,kona-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct platform_driver kona_pwmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "bcm-kona-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .of_match_table = bcm_kona_pwmc_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .probe = kona_pwmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .remove = kona_pwmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) module_platform_driver(kona_pwmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_DESCRIPTION("Broadcom Kona PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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