^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2016 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IPROC_PWM_CTRL_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IPROC_PWM_CTRL_TYPE_SHIFT(ch) (15 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IPROC_PWM_CTRL_POLARITY_SHIFT(ch) (8 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IPROC_PWM_CTRL_EN_SHIFT(ch) (ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IPROC_PWM_PERIOD_OFFSET(ch) (0x04 + ((ch) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IPROC_PWM_PERIOD_MIN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IPROC_PWM_PERIOD_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IPROC_PWM_DUTY_CYCLE_OFFSET(ch) (0x08 + ((ch) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IPROC_PWM_DUTY_CYCLE_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IPROC_PWM_DUTY_CYCLE_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IPROC_PWM_PRESCALE_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IPROC_PWM_PRESCALE_BITS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) IPROC_PWM_PRESCALE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IPROC_PWM_PRESCALE_MASK(ch) (IPROC_PWM_PRESCALE_MAX << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) IPROC_PWM_PRESCALE_SHIFT(ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IPROC_PWM_PRESCALE_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IPROC_PWM_PRESCALE_MAX 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct iproc_pwmc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline struct iproc_pwmc *to_iproc_pwmc(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return container_of(chip, struct iproc_pwmc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void iproc_pwmc_enable(struct iproc_pwmc *ip, unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) value |= 1 << IPROC_PWM_CTRL_EN_SHIFT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* must be a 400 ns delay between clearing and setting enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ndelay(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void iproc_pwmc_disable(struct iproc_pwmc *ip, unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) value &= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* must be a 400 ns delay between clearing and setting enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ndelay(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct iproc_pwmc *ip = to_iproc_pwmc(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u64 tmp, multi, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 value, prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) state->polarity = PWM_POLARITY_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rate = clk_get_rate(ip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (rate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) state->period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) state->duty_cycle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) prescale &= IPROC_PWM_PRESCALE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) multi = NSEC_PER_SEC * (prescale + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) state->period = div64_u64(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) state->duty_cycle = div64_u64(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long prescale = IPROC_PWM_PRESCALE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct iproc_pwmc *ip = to_iproc_pwmc(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 value, period, duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rate = clk_get_rate(ip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Find period count, duty count and prescale to suit duty_cycle and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * period. This is done according to formulas described below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 value, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) div = NSEC_PER_SEC * (prescale + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) value = rate * state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) period = div64_u64(value, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) value = rate * state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) duty = div64_u64(value, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (period < IPROC_PWM_PERIOD_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (period <= IPROC_PWM_PERIOD_MAX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) duty <= IPROC_PWM_DUTY_CYCLE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Otherwise, increase prescale and recalculate counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (++prescale > IPROC_PWM_PRESCALE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) iproc_pwmc_disable(ip, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Set prescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* set period and duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* set polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (state->polarity == PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) value &= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (state->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) iproc_pwmc_enable(ip, pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct pwm_ops iproc_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .apply = iproc_pwmc_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .get_state = iproc_pwmc_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int iproc_pwmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct iproc_pwmc *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ip = devm_kzalloc(&pdev->dev, sizeof(*ip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) platform_set_drvdata(pdev, ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ip->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ip->chip.ops = &iproc_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ip->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ip->chip.npwm = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ip->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ip->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ip->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (IS_ERR(ip->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return PTR_ERR(ip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ip->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (IS_ERR(ip->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(&pdev->dev, "failed to get clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PTR_ERR(ip->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return PTR_ERR(ip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = clk_prepare_enable(ip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Set full drive and normal polarity for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (i = 0; i < ip->chip.npwm; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) value &= ~(1 << IPROC_PWM_CTRL_TYPE_SHIFT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = pwmchip_add(&ip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) clk_disable_unprepare(ip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int iproc_pwmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct iproc_pwmc *ip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clk_disable_unprepare(ip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return pwmchip_remove(&ip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct of_device_id bcm_iproc_pwmc_dt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { .compatible = "brcm,iproc-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DEVICE_TABLE(of, bcm_iproc_pwmc_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct platform_driver iproc_pwmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "bcm-iproc-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .of_match_table = bcm_iproc_pwmc_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .probe = iproc_pwmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .remove = iproc_pwmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) module_platform_driver(iproc_pwmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_DESCRIPTION("Broadcom iProc PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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