^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Atmel Pulse Width Modulation Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Bo Shen <voice.shen@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Links to reference manuals for the supported PWM chips can be found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Documentation/arm/microchip.rst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Limitations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - Periods start with the inactive level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - Hardware has to be stopped in general to update settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Software bugs/possible improvements:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - When atmel_pwm_apply() is called with state->enabled=false a change in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * state->polarity isn't honored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * - Instead of sleeping to wait for a completed period, the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * functionality could be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* The following is global registers for PWM controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PWM_ENA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PWM_DIS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PWM_SR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PWM_ISR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Bit field in SR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PWM_SR_ALL_CH_ON 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* The following register is PWM channel related registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PWM_CH_REG_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWM_CH_REG_SIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PWM_CMR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Bit field in CMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PWM_CMR_CPOL (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PWM_CMR_UPD_CDTY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PWM_CMR_CPRE_MSK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* The following registers for PWM v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PWMV1_CDTY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PWMV1_CPRD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PWMV1_CUPD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* The following registers for PWM v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PWMV2_CDTY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PWMV2_CDTYUPD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PWMV2_CPRD 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PWMV2_CPRDUPD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PWM_MAX_PRES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct atmel_pwm_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 period_upd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 duty_upd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct atmel_pwm_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 period_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct atmel_pwm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct atmel_pwm_registers regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct atmel_pwm_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct atmel_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const struct atmel_pwm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int updated_pwms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* ISR is cleared when read, ensure only one thread does that */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mutex isr_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return container_of(chip, struct atmel_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return readl_relaxed(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long offset, unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel_relaxed(val, chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int ch, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return atmel_pwm_readl(chip, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int ch, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) atmel_pwm_writel(chip, base + offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct pwm_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long *cprd, u32 *pres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long long cycles = state->period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Calculate the period cycles and prescale value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cycles *= clk_get_rate(atmel_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) do_div(cycles, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * The register for the period length is cfg.period_bits bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * So for each bit the number of clock cycles is wider divide the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * clock frequency by two using pres and shift cprd accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (shift > PWM_MAX_PRES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(chip->dev, "pres exceeds the maximum value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } else if (shift > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *pres = shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cycles >>= *pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *pres = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *cprd = cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long cprd, unsigned long *cdty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long long cycles = state->duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cycles *= cprd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) do_div(cycles, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *cdty = cprd - cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long cdty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (atmel_pwm->data->regs.duty_upd ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) atmel_pwm->data->regs.period_upd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val &= ~PWM_CMR_UPD_CDTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) atmel_pwm->data->regs.duty_upd, cdty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long cprd, unsigned long cdty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) atmel_pwm->data->regs.duty, cdty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) atmel_pwm->data->regs.period, cprd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bool disable_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long timeout = jiffies + 2 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Wait for at least a complete period to have passed before disabling a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * channel to be sure that CDTY has been updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mutex_lock(&atmel_pwm->isr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mutex_unlock(&atmel_pwm->isr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Wait for the PWM channel disable operation to be effective before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * stopping the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) timeout = jiffies + 2 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) time_before(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (disable_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clk_disable(atmel_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct pwm_state cstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long cprd, cdty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 pres, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pwm_get_state(pwm, &cstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (cstate.enabled &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) cstate.polarity == state->polarity &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cstate.period == state->period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) atmel_pwm->data->regs.period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) atmel_pwm_calculate_cdty(state, cprd, &cdty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) atmel_pwm_update_cdty(chip, pwm, cdty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) &pres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "failed to calculate cprd and prescaler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) atmel_pwm_calculate_cdty(state, cprd, &cdty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (cstate.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) atmel_pwm_disable(chip, pwm, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = clk_enable(atmel_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_err(chip->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* It is necessary to preserve CPOL, inside CMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (state->polarity == PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) val &= ~PWM_CMR_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val |= PWM_CMR_CPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mutex_lock(&atmel_pwm->isr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mutex_unlock(&atmel_pwm->isr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } else if (cstate.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) atmel_pwm_disable(chip, pwm, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 sr, cmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (sr & (1 << pwm->hwpwm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long rate = clk_get_rate(atmel_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 cdty, cprd, pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pres = cmr & PWM_CMR_CPRE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) atmel_pwm->data->regs.period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tmp = (u64)cprd * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) tmp <<= pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) state->period = DIV64_U64_ROUND_UP(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) atmel_pwm->data->regs.duty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tmp <<= pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) state->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) state->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (cmr & PWM_CMR_CPOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) state->polarity = PWM_POLARITY_INVERSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) state->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct pwm_ops atmel_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .apply = atmel_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .get_state = atmel_pwm_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .period = PWMV1_CPRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .period_upd = PWMV1_CUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .duty = PWMV1_CDTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .duty_upd = PWMV1_CUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* 16 bits to keep period and duty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .period_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct atmel_pwm_data atmel_sama5_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .period = PWMV2_CPRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .period_upd = PWMV2_CPRDUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .duty = PWMV2_CDTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .duty_upd = PWMV2_CDTYUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* 16 bits to keep period and duty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .period_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .period = PWMV1_CPRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .period_upd = PWMV1_CUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .duty = PWMV1_CDTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .duty_upd = PWMV1_CUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* 32 bits to keep period and duty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .period_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct of_device_id atmel_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .compatible = "atmel,at91sam9rl-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .data = &atmel_sam9rl_pwm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .compatible = "atmel,sama5d3-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .data = &atmel_sama5_pwm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .compatible = "atmel,sama5d2-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .data = &atmel_sama5_pwm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .compatible = "microchip,sam9x60-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .data = &mchp_sam9x60_pwm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int atmel_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct atmel_pwm_chip *atmel_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!atmel_pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mutex_init(&atmel_pwm->isr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) atmel_pwm->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) atmel_pwm->updated_pwms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (IS_ERR(atmel_pwm->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return PTR_ERR(atmel_pwm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (IS_ERR(atmel_pwm->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return PTR_ERR(atmel_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = clk_prepare(atmel_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&pdev->dev, "failed to prepare PWM clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) atmel_pwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) atmel_pwm->chip.ops = &atmel_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) atmel_pwm->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) atmel_pwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) atmel_pwm->chip.npwm = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = pwmchip_add(&atmel_pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto unprepare_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) platform_set_drvdata(pdev, atmel_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unprepare_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) clk_unprepare(atmel_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int atmel_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) clk_unprepare(atmel_pwm->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mutex_destroy(&atmel_pwm->isr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return pwmchip_remove(&atmel_pwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct platform_driver atmel_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .name = "atmel-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .probe = atmel_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .remove = atmel_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) module_platform_driver(atmel_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_ALIAS("platform:atmel-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_DESCRIPTION("Atmel PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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