^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Overkiz SAS 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <soc/at91/atmel_tcb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NPWM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct atmel_tcb_pwm_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum pwm_polarity polarity; /* PWM polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned div; /* PWM clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned duty; /* PWM duty expressed in clk cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned period; /* PWM period expressed in clk cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct atmel_tcb_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 cmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 ra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct atmel_tcb_pwm_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct atmel_tc *tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct atmel_tcb_pwm_device *pwms[NPWM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct atmel_tcb_channel bkup[NPWM / 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return container_of(chip, struct atmel_tcb_pwm_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum pwm_polarity polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tcbpwm->polarity = polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int atmel_tcb_pwm_request(struct pwm_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct atmel_tcb_pwm_device *tcbpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct atmel_tc *tc = tcbpwmc->tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __iomem *regs = tc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned group = pwm->hwpwm / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned index = pwm->hwpwm % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned cmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!tcbpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = clk_prepare_enable(tc->clk[group]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) devm_kfree(chip->dev, tcbpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pwm_set_chip_data(pwm, tcbpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tcbpwm->polarity = PWM_POLARITY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tcbpwm->duty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tcbpwm->period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tcbpwm->div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) spin_lock(&tcbpwmc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Get init config from Timer Counter registers if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Timer Counter is already configured as a PWM generator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (cmr & ATMEL_TC_WAVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) tcbpwm->duty =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __raw_readl(regs + ATMEL_TC_REG(group, RA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tcbpwm->duty =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __raw_readl(regs + ATMEL_TC_REG(group, RB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ATMEL_TC_BCMR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cmr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) spin_unlock(&tcbpwmc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct atmel_tc *tc = tcbpwmc->tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk_disable_unprepare(tc->clk[pwm->hwpwm / 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tcbpwmc->pwms[pwm->hwpwm] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) devm_kfree(chip->dev, tcbpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct atmel_tc *tc = tcbpwmc->tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *regs = tc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned group = pwm->hwpwm / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned index = pwm->hwpwm % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned cmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enum pwm_polarity polarity = tcbpwm->polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * If duty is 0 the timer will be stopped and we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * configure the output correctly on software trigger:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * - set output to high if PWM_POLARITY_INVERSED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * - set output to low if PWM_POLARITY_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * This is why we're reverting polarity in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (tcbpwm->duty == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) polarity = !polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_lock(&tcbpwmc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* flush old setting and set the new one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) cmr &= ~ATMEL_TC_ACMR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cmr |= ATMEL_TC_ASWTRG_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cmr |= ATMEL_TC_ASWTRG_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cmr &= ~ATMEL_TC_BCMR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cmr |= ATMEL_TC_BSWTRG_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cmr |= ATMEL_TC_BSWTRG_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Use software trigger to apply the new setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * If both PWM devices in this group are disabled we stop the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __raw_writel(ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) regs + ATMEL_TC_REG(group, CCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tcbpwmc->bkup[group].enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) __raw_writel(ATMEL_TC_SWTRG, regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ATMEL_TC_REG(group, CCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tcbpwmc->bkup[group].enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spin_unlock(&tcbpwmc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct atmel_tc *tc = tcbpwmc->tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *regs = tc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned group = pwm->hwpwm / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned index = pwm->hwpwm % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 cmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum pwm_polarity polarity = tcbpwm->polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * If duty is 0 the timer will be stopped and we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * configure the output correctly on software trigger:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * - set output to high if PWM_POLARITY_INVERSED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * - set output to low if PWM_POLARITY_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * This is why we're reverting polarity in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (tcbpwm->duty == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) polarity = !polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) spin_lock(&tcbpwmc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* flush old setting and set the new one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cmr &= ~ATMEL_TC_TCCLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cmr &= ~ATMEL_TC_ACMR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Set CMR flags according to given polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cmr |= ATMEL_TC_ASWTRG_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) cmr |= ATMEL_TC_ASWTRG_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) cmr &= ~ATMEL_TC_BCMR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cmr |= ATMEL_TC_BSWTRG_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cmr |= ATMEL_TC_BSWTRG_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * If duty is 0 or equal to period there's no need to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * a specific action on RA/RB and RC compare.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * The output will be configured on software trigger and keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * this config till next config call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (polarity == PWM_POLARITY_INVERSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __raw_writel(tcbpwm->period, regs + ATMEL_TC_REG(group, RC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Use software trigger to apply the new setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) regs + ATMEL_TC_REG(group, CCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tcbpwmc->bkup[group].enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) spin_unlock(&tcbpwmc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int duty_ns, int period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned group = pwm->hwpwm / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned index = pwm->hwpwm % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct atmel_tcb_pwm_device *atcbpwm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct atmel_tc *tc = tcbpwmc->tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int slowclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned rate = clk_get_rate(tc->clk[group]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned long long min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long long max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Find best clk divisor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * the smallest divisor which can fulfill the period_ns requirements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < 5; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (atmel_tc_divisors[i] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) slowclk = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) min = div_u64((u64)NSEC_PER_SEC * atmel_tc_divisors[i], rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) max = min << tc->tcb_config->counter_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (max >= period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * If none of the divisor are small enough to represent period_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * take slow clock (32KHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (i == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) i = slowclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) rate = clk_get_rate(tc->slow_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) min = div_u64(NSEC_PER_SEC, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) max = min << tc->tcb_config->counter_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* If period is too big return ERANGE error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (max < period_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) duty = div_u64(duty_ns, min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) period = div_u64(period_ns, min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) atcbpwm = tcbpwmc->pwms[pwm->hwpwm + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) atcbpwm = tcbpwmc->pwms[pwm->hwpwm - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * PWM devices provided by TCB driver are grouped by 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * - group 0: PWM 0 & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * - group 1: PWM 2 & 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * - group 2: PWM 4 & 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * PWM devices in a given group must be configured with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * same period_ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * We're checking the period value of the second PWM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * in this group before applying the new config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if ((atcbpwm && atcbpwm->duty > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) atcbpwm->duty != atcbpwm->period) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (atcbpwm->div != i || atcbpwm->period != period)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "failed to configure period_ns: PWM group already configured with a different value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tcbpwm->period = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) tcbpwm->div = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) tcbpwm->duty = duty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* If the PWM is enabled, call enable to apply the new conf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (pwm_is_enabled(pwm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) atmel_tcb_pwm_enable(chip, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct pwm_ops atmel_tcb_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .request = atmel_tcb_pwm_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .free = atmel_tcb_pwm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .config = atmel_tcb_pwm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .set_polarity = atmel_tcb_pwm_set_polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .enable = atmel_tcb_pwm_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .disable = atmel_tcb_pwm_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int atmel_tcb_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct atmel_tcb_pwm_chip *tcbpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct atmel_tc *tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int tcblock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) err = of_property_read_u32(np, "tc-block", &tcblock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "failed to get Timer Counter Block number from device tree (error: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) tc = atmel_tc_alloc(tcblock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (tc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (tcbpwm == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto err_free_tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tcbpwm->chip.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) tcbpwm->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) tcbpwm->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tcbpwm->chip.npwm = NPWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) tcbpwm->tc = tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) err = clk_prepare_enable(tc->slow_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto err_free_tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spin_lock_init(&tcbpwm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) err = pwmchip_add(&tcbpwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) platform_set_drvdata(pdev, tcbpwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) clk_disable_unprepare(tcbpwm->tc->slow_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err_free_tc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) atmel_tc_free(tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int atmel_tcb_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) clk_disable_unprepare(tcbpwm->tc->slow_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) err = pwmchip_remove(&tcbpwm->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) atmel_tc_free(tcbpwm->tc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { .compatible = "atmel,tcb-pwm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int atmel_tcb_pwm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void __iomem *base = tcbpwm->tc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) for (i = 0; i < (NPWM / 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct atmel_tcb_channel *chan = &tcbpwm->bkup[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) chan->cmr = readl(base + ATMEL_TC_REG(i, CMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) chan->ra = readl(base + ATMEL_TC_REG(i, RA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) chan->rb = readl(base + ATMEL_TC_REG(i, RB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) chan->rc = readl(base + ATMEL_TC_REG(i, RC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int atmel_tcb_pwm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) void __iomem *base = tcbpwm->tc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) for (i = 0; i < (NPWM / 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct atmel_tcb_channel *chan = &tcbpwm->bkup[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) writel(chan->cmr, base + ATMEL_TC_REG(i, CMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) writel(chan->ra, base + ATMEL_TC_REG(i, RA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writel(chan->rb, base + ATMEL_TC_REG(i, RB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) writel(chan->rc, base + ATMEL_TC_REG(i, RC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (chan->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) base + ATMEL_TC_REG(i, CCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) atmel_tcb_pwm_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static struct platform_driver atmel_tcb_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .name = "atmel-tcb-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .of_match_table = atmel_tcb_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .pm = &atmel_tcb_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .probe = atmel_tcb_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .remove = atmel_tcb_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) module_platform_driver(atmel_tcb_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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