^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/atmel-hlcdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ATMEL_HLCDC_PWMCVAL(x) (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ATMEL_HLCDC_PWMPOL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ATMEL_HLCDC_PWMPS_MAX 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ATMEL_HLCDC_PWMPS(x) ((x) & ATMEL_HLCDC_PWMPS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct atmel_hlcdc_pwm_errata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) bool slow_clk_erratum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bool div1_clk_erratum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct atmel_hlcdc_pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct pwm_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct atmel_hlcdc *hlcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk *cur_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct atmel_hlcdc_pwm_errata *errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return container_of(chip, struct atmel_hlcdc_pwm, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int atmel_hlcdc_pwm_apply(struct pwm_chip *c, struct pwm_device *pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const struct pwm_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct atmel_hlcdc *hlcdc = chip->hlcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (state->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk *new_clk = hlcdc->slow_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u64 pwmcval = state->duty_cycle * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u64 clk_period_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 pwmcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!chip->errata || !chip->errata->slow_clk_erratum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clk_freq = clk_get_rate(new_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!clk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clk_period_ns = (u64)NSEC_PER_SEC * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) do_div(clk_period_ns, clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Errata: cannot use slow clk on some IP revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if ((chip->errata && chip->errata->slow_clk_erratum) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) clk_period_ns > state->period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) new_clk = hlcdc->sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk_freq = clk_get_rate(new_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!clk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clk_period_ns = (u64)NSEC_PER_SEC * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) do_div(clk_period_ns, clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Errata: cannot divide by 1 on some IP revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!pres && chip->errata &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) chip->errata->div1_clk_erratum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if ((clk_period_ns << pres) >= state->period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (pres > ATMEL_HLCDC_PWMPS_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pwmcfg = ATMEL_HLCDC_PWMPS(pres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (new_clk != chip->cur_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 gencfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = clk_prepare_enable(new_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk_disable_unprepare(chip->cur_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) chip->cur_clk = new_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (new_clk == hlcdc->sys_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) gencfg = ATMEL_HLCDC_CLKPWMSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = regmap_update_bits(hlcdc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ATMEL_HLCDC_CFG(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ATMEL_HLCDC_CLKPWMSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) gencfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) do_div(pwmcval, state->period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * The PWM duty cycle is configurable from 0/256 to 255/256 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * the period cycle. Hence we can't set a duty cycle occupying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * the whole period cycle if we're asked to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Set it to 255 if pwmcval is greater than 256.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (pwmcval > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pwmcval = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (state->polarity == PWM_POLARITY_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pwmcfg |= ATMEL_HLCDC_PWMPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ATMEL_HLCDC_PWMCVAL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ATMEL_HLCDC_PWMPS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ATMEL_HLCDC_PWMPOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pwmcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ATMEL_HLCDC_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) status & ATMEL_HLCDC_PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ATMEL_HLCDC_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) !(status & ATMEL_HLCDC_PWM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 10, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clk_disable_unprepare(chip->cur_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) chip->cur_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct pwm_ops atmel_hlcdc_pwm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .apply = atmel_hlcdc_pwm_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .slow_clk_erratum = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .div1_clk_erratum = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int atmel_hlcdc_pwm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct atmel_hlcdc_pwm *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Keep the periph clock enabled if the PWM is still running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (pwm_is_enabled(&chip->chip.pwms[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk_disable_unprepare(chip->hlcdc->periph_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int atmel_hlcdc_pwm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct atmel_hlcdc_pwm *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct pwm_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pwm_get_state(&chip->chip.pwms[0], &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Re-enable the periph clock it was stopped during suspend. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!state.enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = clk_prepare_enable(chip->hlcdc->periph_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return atmel_hlcdc_pwm_apply(&chip->chip, &chip->chip.pwms[0], &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static SIMPLE_DEV_PM_OPS(atmel_hlcdc_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) atmel_hlcdc_pwm_suspend, atmel_hlcdc_pwm_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct of_device_id atmel_hlcdc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .compatible = "atmel,at91sam9n12-hlcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* 9n12 has same errata as 9x5 HLCDC PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .compatible = "atmel,at91sam9x5-hlcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .data = &atmel_hlcdc_pwm_at91sam9x5_errata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .compatible = "atmel,sama5d2-hlcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .compatible = "atmel,sama5d3-hlcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .data = &atmel_hlcdc_pwm_sama5d3_errata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .compatible = "atmel,sama5d4-hlcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .data = &atmel_hlcdc_pwm_sama5d3_errata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .compatible = "microchip,sam9x60-hlcdc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct atmel_hlcdc_pwm *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct atmel_hlcdc *hlcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) hlcdc = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = clk_prepare_enable(hlcdc->periph_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) chip->errata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) chip->hlcdc = hlcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) chip->chip.ops = &atmel_hlcdc_pwm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) chip->chip.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) chip->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) chip->chip.npwm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) chip->chip.of_xlate = of_pwm_xlate_with_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) chip->chip.of_pwm_n_cells = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = pwmchip_add_with_polarity(&chip->chip, PWM_POLARITY_INVERSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk_disable_unprepare(hlcdc->periph_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int atmel_hlcdc_pwm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct atmel_hlcdc_pwm *chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = pwmchip_remove(&chip->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clk_disable_unprepare(chip->hlcdc->periph_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { .compatible = "atmel,hlcdc-pwm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct platform_driver atmel_hlcdc_pwm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "atmel-hlcdc-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .of_match_table = atmel_hlcdc_pwm_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .pm = &atmel_hlcdc_pwm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .probe = atmel_hlcdc_pwm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .remove = atmel_hlcdc_pwm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) module_platform_driver(atmel_hlcdc_pwm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_ALIAS("platform:atmel-hlcdc-pwm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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